Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	445	1			T74	1		T222	1		T402	2
all_values[1]	426	1			T74	3		T222	1		T402	1
all_values[2]	470	1			T74	4		T222	1		T402	1
all_values[3]	459	1			T74	2		T402	1		T403	1
all_values[4]	480	1			T222	1		T403	4		T504	5
all_values[5]	494	1			T74	6		T222	1		T388	1
all_values[6]	461	1			T74	2		T504	2		T686	2
all_values[7]	491	1			T402	1		T403	3		T504	3
all_values[8]	433	1			T74	2		T388	1		T403	1
all_values[9]	519	1			T74	3		T222	1		T402	3
all_values[10]	481	1			T74	2		T222	1		T402	1
all_values[11]	455	1			T74	3		T222	1		T402	2
all_values[12]	493	1			T74	9		T222	1		T402	3
all_values[13]	469	1			T74	4		T222	1		T402	2
all_values[14]	461	1			T504	2		T399	4		T503	1
all_values[15]	473	1			T74	2		T222	1		T403	2
all_values[16]	463	1			T74	1		T402	1		T403	1
all_values[17]	501	1			T74	1		T388	1		T403	2
all_values[18]	469	1			T74	2		T388	1		T504	3
all_values[19]	465	1			T71	1		T74	4		T402	2
all_values[20]	490	1			T74	2		T222	1		T402	1
all_values[21]	477	1			T71	1		T74	3		T402	2
all_values[22]	502	1			T74	5		T402	1		T403	2
all_values[23]	433	1			T74	2		T402	1		T504	3
all_values[24]	456	1			T74	4		T222	1		T403	2
all_values[25]	478	1			T74	1		T403	1		T504	6
all_values[26]	487	1			T74	2		T403	2		T504	2
all_values[27]	455	1			T74	3		T402	2		T403	1
all_values[28]	482	1			T74	2		T402	2		T388	1
all_values[29]	521	1			T74	6		T222	1		T402	1
all_values[30]	467	1			T74	1		T402	1		T403	2
all_values[31]	471	1			T74	2		T402	1		T403	5
all_values[32]	525	1			T74	7		T402	1		T504	1
all_values[33]	475	1			T74	2		T402	2		T388	1
all_values[34]	477	1			T71	1		T74	5		T403	1
all_values[35]	472	1			T74	1		T402	1		T388	1
all_values[36]	489	1			T71	1		T74	2		T222	1
all_values[37]	457	1			T74	2		T402	3		T403	1
all_values[38]	506	1			T74	2		T402	2		T388	1
all_values[39]	513	1			T74	8		T402	2		T388	2
all_values[40]	462	1			T74	3		T403	2		T504	2
all_values[41]	486	1			T71	1		T74	2		T403	1
all_values[42]	458	1			T74	1		T388	1		T504	2
all_values[43]	515	1			T74	4		T222	1		T402	1
all_values[44]	480	1			T74	6		T402	1		T403	3
all_values[45]	451	1			T403	2		T504	1		T399	4
all_values[46]	465	1			T74	6		T402	1		T403	1
all_values[47]	528	1			T74	5		T388	1		T504	3
all_values[48]	448	1			T222	1		T388	1		T399	3
all_values[49]	428	1			T222	1		T403	1		T399	5