Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3609	1			T74	32		T222	3		T418	1
all_values[1]	3669	1			T74	40		T222	1		T418	2
all_values[2]	3577	1			T74	34		T222	2		T418	1
all_values[3]	3626	1			T74	38		T222	5		T418	1
all_values[4]	3654	1			T74	34		T222	3		T418	1
all_values[5]	3652	1			T74	36		T222	2		T402	5
all_values[6]	3589	1			T74	39		T222	2		T418	2
all_values[7]	3632	1			T74	42		T222	4		T418	2
all_values[8]	3681	1			T74	30		T222	5		T418	1
all_values[9]	3599	1			T74	34		T222	3		T418	3
all_values[10]	3535	1			T74	29		T222	3		T418	1
all_values[11]	3700	1			T74	25		T222	4		T418	1
all_values[12]	3640	1			T74	25		T222	5		T418	3
all_values[13]	3493	1			T74	37		T222	3		T418	6
all_values[14]	3683	1			T74	30		T222	1		T418	1
all_values[15]	3601	1			T74	49		T222	2		T418	1
all_values[16]	3625	1			T74	32		T222	1		T418	1
all_values[17]	3622	1			T74	40		T222	2		T418	1
all_values[18]	3640	1			T74	33		T222	2		T418	2
all_values[19]	3585	1			T74	24		T222	1		T418	2
all_values[20]	3621	1			T74	29		T222	2		T418	2
all_values[21]	3634	1			T74	29		T222	3		T418	3
all_values[22]	3562	1			T74	41		T222	1		T418	2
all_values[23]	3624	1			T74	30		T222	1		T418	2
all_values[24]	3561	1			T74	32		T222	3		T418	1
all_values[25]	3655	1			T74	29		T222	4		T418	2
all_values[26]	3583	1			T74	34		T418	1		T402	4
all_values[27]	3627	1			T74	35		T222	2		T402	10
all_values[28]	3708	1			T74	27		T222	3		T418	5
all_values[29]	3601	1			T74	33		T222	2		T418	3
all_values[30]	3601	1			T74	33		T222	1		T418	6
all_values[31]	3583	1			T74	44		T222	1		T418	3
all_values[32]	3663	1			T74	38		T222	8		T418	2
all_values[33]	3656	1			T74	42		T222	3		T418	4
all_values[34]	3619	1			T74	33		T222	7		T418	1
all_values[35]	3657	1			T74	24		T222	4		T418	3
all_values[36]	3559	1			T74	37		T222	5		T402	1
all_values[37]	3633	1			T74	35		T222	1		T418	2
all_values[38]	3515	1			T74	35		T222	3		T418	3
all_values[39]	3671	1			T74	33		T222	3		T418	1
all_values[40]	3603	1			T74	29		T418	1		T402	7
all_values[41]	3639	1			T74	34		T222	1		T418	2
all_values[42]	3644	1			T74	30		T222	2		T418	2
all_values[43]	3611	1			T74	32		T222	3		T418	1
all_values[44]	3661	1			T74	45		T222	2		T418	2
all_values[45]	3524	1			T74	41		T418	2		T402	4
all_values[46]	3640	1			T74	35		T222	2		T418	4
all_values[47]	3573	1			T74	33		T222	4		T418	1
all_values[48]	3766	1			T74	40		T222	1		T402	8
all_values[49]	3498	1			T74	40		T418	2		T402	9
all_values[50]	3660	1			T74	38		T222	3		T418	4
all_values[51]	3628	1			T74	29		T222	5		T402	3
all_values[52]	3637	1			T74	31		T418	1		T402	2
all_values[53]	3646	1			T74	35		T222	3		T418	1
all_values[54]	3646	1			T74	38		T222	2		T418	2
all_values[55]	3681	1			T74	31		T222	1		T418	1
all_values[56]	3578	1			T74	35		T222	2		T418	1
all_values[57]	3658	1			T74	35		T222	3		T418	2
all_values[58]	3640	1			T74	31		T222	6		T418	4
all_values[59]	3627	1			T74	38		T222	3		T418	2
all_values[60]	3668	1			T74	38		T222	6		T418	1
all_values[61]	3642	1			T74	43		T222	2		T418	1
all_values[62]	3741	1			T74	43		T222	4		T402	6
all_values[63]	3662	1			T74	31		T222	2		T418	2