Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	131671	1			T69	88		T70	10		T76	4
values[2]	7919	1			T69	4		T70	1		T77	2
values[3]	3101	1			T463	1		T522	1		T521	1
values[4]	1891	1			T522	1		T391	22		T836	6
values[5]	1272	1			T522	1		T391	4		T836	11
values[6]	915	1			T522	1		T836	2		T477	3
values[7]	584	1			T522	1		T836	4		T477	6
values[8]	458	1			T522	1		T836	4		T477	4
values[9]	405	1			T522	1		T836	1		T477	9
values[10]	383	1			T522	1		T836	1		T477	6
values[11]	314	1			T522	1		T836	3		T477	5
values[12]	333	1			T522	1		T836	2		T477	11
values[13]	270	1			T522	1		T836	1		T477	9
values[14]	230	1			T522	1		T836	2		T477	7
values[15]	274	1			T522	1		T836	1		T477	9
values[16]	282	1			T522	1		T836	1		T477	3
values[17]	281	1			T522	1		T836	8		T477	13
values[18]	265	1			T522	1		T836	2		T477	5
values[19]	238	1			T522	1		T836	1		T477	14
values[20]	250	1			T522	1		T836	2		T477	14
values[21]	261	1			T522	1		T836	3		T477	3
values[22]	246	1			T522	1		T836	4		T477	5
values[23]	240	1			T522	1		T836	2		T477	9
values[24]	263	1			T522	1		T836	3		T477	6
values[25]	246	1			T522	1		T836	1		T477	3
values[26]	259	1			T522	1		T836	2		T477	8
values[27]	249	1			T522	1		T836	1		T477	9
values[28]	240	1			T522	1		T836	2		T477	23
values[29]	221	1			T522	1		T836	5		T477	4
values[30]	259	1			T522	1		T836	4		T477	5
values[31]	248	1			T522	1		T836	3		T477	15
values[32]	266	1			T522	1		T836	6		T477	9
values[33]	231	1			T522	1		T836	5		T477	2
values[34]	214	1			T522	1		T836	5		T477	4
values[35]	275	1			T522	1		T836	4		T477	4
values[36]	246	1			T522	1		T836	3		T477	7
values[37]	250	1			T522	1		T836	8		T477	4
values[38]	224	1			T522	1		T836	4		T477	6
values[39]	207	1			T522	1		T836	3		T477	4
values[40]	219	1			T522	1		T836	5		T477	4
values[41]	226	1			T522	1		T836	3		T477	12
values[42]	248	1			T522	1		T836	8		T477	6
values[43]	209	1			T522	1		T836	3		T477	26
values[44]	235	1			T522	1		T836	6		T477	14
values[45]	197	1			T522	1		T836	1		T477	5
values[46]	201	1			T522	1		T836	3		T477	4
values[47]	215	1			T522	1		T836	4		T477	3
values[48]	263	1			T522	1		T836	6		T477	9
values[49]	261	1			T522	1		T836	5		T477	5
values[50]	214	1			T522	1		T836	2		T477	4
values[51]	251	1			T522	1		T836	1		T477	8
values[52]	208	1			T522	1		T836	3		T477	9
values[53]	184	1			T522	1		T836	4		T477	10
values[54]	233	1			T522	1		T836	2		T477	16
values[55]	195	1			T522	1		T836	1		T477	10
values[56]	197	1			T522	1		T836	7		T477	14
values[57]	178	1			T522	1		T836	2		T477	9
values[58]	183	1			T522	1		T836	2		T477	4
values[59]	155	1			T522	1		T836	2		T477	6
values[60]	136	1			T522	1		T836	5		T477	5
values[61]	134	1			T522	1		T836	4		T477	9
values[62]	129	1			T522	1		T836	2		T477	5
values[63]	121	1			T522	1		T836	3		T477	4
values[64]	119	1			T522	1		T836	4		T477	5
values[65]	100	1			T522	1		T836	12		T477	5
values[66]	100	1			T522	1		T836	17		T429	4
values[67]	96	1			T522	1		T836	15		T429	5
values[68]	115	1			T522	2		T836	6		T429	5
values[69]	129	1			T522	1		T836	16		T429	7
values[70]	116	1			T522	1		T836	10		T429	11
values[71]	105	1			T522	1		T836	3		T429	1
values[72]	73	1			T522	1		T836	6		T856	1
values[73]	78	1			T522	1		T836	3		T856	1
values[74]	105	1			T522	1		T836	12		T856	1
values[75]	85	1			T522	1		T836	3		T856	1
values[76]	106	1			T522	1		T836	10		T856	1
values[77]	83	1			T522	1		T836	4		T856	1
values[78]	98	1			T522	1		T836	14		T856	1
values[79]	72	1			T522	1		T836	7		T856	1
values[80]	81	1			T522	1		T836	2		T856	1
values[81]	91	1			T522	1		T836	5		T856	1
values[82]	70	1			T522	2		T836	1		T856	1
values[83]	76	1			T522	1		T836	2		T856	1
values[84]	59	1			T522	1		T836	3		T856	1
values[85]	74	1			T522	1		T836	6		T856	1
values[86]	73	1			T522	1		T836	3		T856	1
values[87]	63	1			T522	1		T836	3		T856	1
values[88]	60	1			T522	1		T836	3		T856	1
values[89]	62	1			T522	1		T836	6		T856	1
values[90]	55	1			T522	1		T836	3		T856	1
values[91]	59	1			T522	1		T836	2		T856	1
values[92]	89	1			T522	1		T836	12		T856	1
values[93]	77	1			T522	1		T836	7		T856	1
values[94]	79	1			T522	1		T836	6		T856	1
values[95]	80	1			T522	1		T836	8		T856	1
values[96]	83	1			T522	1		T836	3		T856	1
values[97]	80	1			T522	1		T836	8		T856	1
values[98]	106	1			T522	1		T836	13		T856	1
values[99]	81	1			T522	1		T836	6		T856	2
values[100]	67	1			T522	1		T836	8		T856	1
values[101]	61	1			T522	1		T836	1		T856	1
values[102]	75	1			T522	1		T836	3		T856	1
values[103]	78	1			T522	1		T836	5		T856	1
values[104]	63	1			T522	1		T836	2		T856	1
values[105]	75	1			T522	1		T836	5		T856	1
values[106]	118	1			T522	1		T836	14		T856	1
values[107]	83	1			T522	1		T836	13		T856	1
values[108]	67	1			T522	1		T836	3		T856	1
values[109]	64	1			T522	1		T836	6		T856	1
values[110]	72	1			T522	1		T836	5		T856	1
values[111]	83	1			T522	1		T836	7		T856	1
values[112]	78	1			T522	1		T836	5		T856	1
values[113]	88	1			T522	1		T836	2		T856	1
values[114]	73	1			T522	1		T836	1		T856	1
values[115]	74	1			T522	1		T856	1		T851	2
values[116]	68	1			T522	1		T856	1		T851	1
values[117]	60	1			T522	1		T856	1		T851	2
values[118]	65	1			T522	1		T856	1		T851	1
values[119]	55	1			T522	1		T856	2		T851	2
values[120]	54	1			T522	1		T856	4		T851	2
values[121]	85	1			T522	4		T856	5		T851	3
values[122]	84	1			T522	2		T856	5		T851	1
values[123]	61	1			T522	2		T856	5		T851	1
values[124]	60	1			T522	2		T856	1		T851	1
values[125]	79	1			T522	1		T856	4		T851	1
values[126]	103	1			T522	3		T856	3		T851	1
values[127]	565	1			T522	32		T856	39		T851	26
values[128]	4641	1			T522	298		T856	385		T851	335