Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.89	95.27	93.76	95.04		94.38	97.38	99.53

Total tests in report: 2831

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.52	40.52	45.93	45.93	43.22	43.22	32.26	32.26			58.30	58.30	63.03	63.03	0.39	0.39	/workspace/coverage/default/48.chip_sw_all_escalation_resets.4059648525
50.27	9.75	51.78	5.85	58.05	14.84	33.64	1.38			69.42	11.11	87.43	24.40	1.33	0.94	/workspace/coverage/cover_reg_top/1.chip_csr_rw.278810540
56.56	6.28	62.46	10.69	59.38	1.33	36.57	2.93			69.51	0.10	87.43	0.00	23.98	22.65	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.499397750
62.12	5.56	74.50	12.04	67.42	8.04	39.17	2.60			80.19	10.68	87.43	0.00	23.98	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2448665226
65.48	3.37	74.50	0.00	67.42	0.01	39.17	0.00			80.19	0.00	87.43	0.00	44.19	20.21	/workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3578102791
68.23	2.74	74.51	0.01	67.45	0.02	55.58	16.42			80.21	0.02	87.43	0.00	44.19	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3253428847
70.88	2.65	76.37	1.86	69.87	2.43	64.77	9.18			82.07	1.86	87.99	0.55	44.19	0.00	/workspace/coverage/default/1.rom_raw_unlock.4246538070
73.26	2.38	81.80	5.43	73.75	3.88	68.23	3.46			83.60	1.53	87.99	0.00	44.19	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2532064386
75.57	2.31	81.80	0.00	74.29	0.54	68.33	0.10			83.60	0.00	87.99	0.00	57.40	13.21	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2581838503
77.60	2.03	83.90	2.09	74.97	0.68	72.88	4.55			83.82	0.21	87.99	0.00	62.05	4.65	/workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3364274576
79.62	2.02	83.90	0.00	74.97	0.00	72.88	0.00			83.82	0.00	87.99	0.00	74.15	12.10	/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3432233004
81.43	1.81	85.83	1.93	76.41	1.44	74.77	1.88			85.32	1.50	92.05	4.07	74.20	0.05	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4263701464
82.77	1.34	87.77	1.94	79.43	3.02	75.01	0.24			88.17	2.85	92.05	0.00	74.20	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1940056106
83.88	1.11	89.54	1.78	80.85	1.42	76.73	1.72			89.91	1.74	92.05	0.00	74.20	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1468881074
84.92	1.04	89.54	0.00	80.85	0.00	76.73	0.00			89.91	0.00	92.05	0.00	80.45	6.25	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3077876754
85.87	0.95	89.54	0.00	81.60	0.75	76.73	0.00			89.96	0.05	92.05	0.00	85.35	4.90	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.4133141595
86.73	0.86	90.29	0.74	81.76	0.15	76.75	0.02			90.12	0.16	96.12	4.07	85.35	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.150300774
87.40	0.67	90.29	0.00	81.76	0.00	80.74	4.00			90.12	0.00	96.12	0.00	85.40	0.05	/workspace/coverage/default/1.chip_sw_edn_kat.525435905
88.01	0.60	91.23	0.94	82.87	1.11	81.35	0.61			91.08	0.96	96.12	0.00	85.40	0.00	/workspace/coverage/default/2.chip_sw_gpio.3930236895
88.59	0.58	91.28	0.05	82.93	0.06	82.67	1.32			91.08	0.00	96.12	0.00	87.48	2.08	/workspace/coverage/default/2.chip_sw_alert_test.4222260228
89.13	0.54	91.28	0.00	83.38	0.45	82.67	0.00			91.08	0.00	96.12	0.00	90.26	2.78	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3213166112
89.64	0.51	92.27	0.99	84.36	0.98	83.06	0.39			91.74	0.67	96.12	0.00	90.27	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4160735342
90.13	0.49	92.27	0.01	84.48	0.13	83.77	0.71			91.78	0.03	96.12	0.00	92.36	2.09	/workspace/coverage/cover_reg_top/14.xbar_error_random.354419601
90.61	0.48	92.28	0.01	86.94	2.46	83.77	0.00			91.78	0.00	96.12	0.00	92.77	0.41	/workspace/coverage/cover_reg_top/25.chip_tl_errors.3503956103
91.06	0.45	92.84	0.56	87.46	0.52	84.87	1.11			92.27	0.49	96.12	0.00	92.77	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2499890271
91.50	0.44	92.87	0.03	87.50	0.04	87.47	2.60			92.27	0.00	96.12	0.00	92.77	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2286373834
91.92	0.42	93.46	0.60	89.15	1.64	87.50	0.04			92.49	0.22	96.12	0.00	92.77	0.00	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2689416652
92.32	0.41	93.46	0.00	89.15	0.01	87.50	0.00			92.49	0.00	96.12	0.00	95.22	2.44	/workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.958971353
92.65	0.33	93.46	0.00	89.15	0.00	87.50	0.00			92.49	0.00	96.12	0.00	97.17	1.95	/workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.2840947962
92.91	0.26	93.46	0.00	89.15	0.00	89.03	1.52			92.49	0.00	96.12	0.00	97.22	0.05	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.408045949
93.11	0.20	93.72	0.25	89.39	0.24	89.42	0.39			92.80	0.30	96.12	0.00	97.22	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.468257760
93.27	0.16	93.78	0.06	89.80	0.41	89.48	0.06			93.23	0.43	96.12	0.00	97.22	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1586894811
93.41	0.14	93.79	0.01	89.80	0.01	90.23	0.75			93.23	0.00	96.12	0.00	97.26	0.05	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.328907524
93.54	0.13	93.91	0.11	89.95	0.15	90.71	0.49			93.28	0.05	96.12	0.00	97.26	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.1854098472
93.67	0.13	93.91	0.00	90.05	0.10	90.71	0.00			93.29	0.02	96.12	0.00	97.92	0.66	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.508198701
93.79	0.12	94.08	0.17	90.32	0.27	91.00	0.28			93.29	0.00	96.12	0.00	97.92	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2749299342
93.90	0.11	94.08	0.00	90.32	0.00	91.65	0.65			93.29	0.00	96.12	0.00	97.96	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2342417490
94.00	0.10	94.13	0.05	90.39	0.06	92.07	0.43			93.33	0.04	96.12	0.00	97.97	0.01	/workspace/coverage/default/2.rom_e2e_shutdown_output.631951286
94.09	0.09	94.13	0.00	90.58	0.19	92.07	0.00			93.40	0.07	96.12	0.00	98.24	0.27	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.275917500
94.17	0.08	94.13	0.00	90.58	0.00	92.57	0.50			93.40	0.00	96.12	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3132129882
94.25	0.08	94.13	0.00	91.05	0.47	92.57	0.00			93.40	0.00	96.12	0.00	98.24	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.1033154348
94.33	0.08	94.19	0.05	91.13	0.08	92.81	0.24			93.48	0.08	96.12	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2314401234
94.40	0.07	94.19	0.00	91.13	0.00	93.25	0.44			93.48	0.00	96.12	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2754096843
94.47	0.07	94.19	0.01	91.32	0.19	93.25	0.00			93.70	0.21	96.12	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2672322124
94.53	0.07	94.27	0.08	91.46	0.14	93.36	0.11			93.75	0.06	96.12	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1165608796
94.60	0.06	94.39	0.12	91.55	0.09	93.43	0.07			93.85	0.10	96.12	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1249112618
94.65	0.06	94.45	0.07	91.72	0.17	93.43	0.00			93.97	0.12	96.12	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.990066944
94.71	0.06	94.49	0.04	91.96	0.24	93.43	0.00			94.04	0.07	96.12	0.00	98.24	0.00	/workspace/coverage/cover_reg_top/15.chip_csr_rw.2791369383
94.77	0.05	94.51	0.01	92.00	0.04	93.47	0.04			94.07	0.02	96.30	0.18	98.25	0.01	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2803975499
94.82	0.05	94.51	0.00	92.00	0.00	93.79	0.32			94.07	0.00	96.30	0.00	98.25	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3534766636
94.87	0.05	94.51	0.00	92.31	0.31	93.79	0.00			94.07	0.00	96.30	0.00	98.25	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.2397921730
94.91	0.04	94.53	0.02	92.34	0.03	93.79	0.00			94.08	0.02	96.49	0.18	98.26	0.01	/workspace/coverage/default/66.chip_sw_all_escalation_resets.3353478181
94.96	0.04	94.53	0.01	92.35	0.01	93.82	0.04			94.09	0.01	96.67	0.18	98.27	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.2674610486
95.00	0.04	94.54	0.01	92.37	0.01	93.82	0.00			94.12	0.02	96.86	0.18	98.28	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2867259188
95.04	0.04	94.57	0.03	92.37	0.01	93.82	0.01			94.13	0.01	97.04	0.18	98.30	0.01	/workspace/coverage/default/6.chip_sw_all_escalation_resets.486952495
95.08	0.04	94.57	0.01	92.38	0.01	93.83	0.01			94.13	0.01	97.23	0.18	98.31	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.3659036182
95.11	0.03	94.57	0.00	92.39	0.01	93.84	0.01			94.13	0.00	97.41	0.18	98.31	0.00	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1297189556
95.14	0.03	94.57	0.00	92.39	0.00	94.01	0.17			94.13	0.00	97.41	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2694499595
95.16	0.03	94.65	0.08	92.39	0.00	94.08	0.07			94.14	0.01	97.41	0.00	98.31	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.4184873353
95.19	0.02	94.66	0.01	92.42	0.03	94.16	0.08			94.16	0.02	97.41	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2410432026
95.21	0.02	94.73	0.07	92.47	0.05	94.16	0.00			94.17	0.02	97.41	0.00	98.31	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1274772671
95.23	0.02	94.76	0.03	92.50	0.03	94.21	0.04			94.20	0.02	97.41	0.00	98.31	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2646196571
95.25	0.02	94.76	0.00	92.63	0.13	94.21	0.00			94.20	0.00	97.41	0.00	98.31	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.779252643
95.28	0.02	94.76	0.00	92.67	0.03	94.21	0.00			94.22	0.02	97.41	0.00	98.39	0.08	/workspace/coverage/cover_reg_top/36.xbar_access_same_device.4105948360
95.30	0.02	94.76	0.00	92.67	0.00	94.33	0.12			94.22	0.00	97.41	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2804869824
95.32	0.02	94.76	0.00	92.67	0.00	94.45	0.12			94.22	0.00	97.41	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.4251131875
95.34	0.02	94.81	0.05	92.69	0.03	94.46	0.01			94.25	0.03	97.41	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2831671233
95.35	0.02	94.81	0.00	92.80	0.11	94.46	0.00			94.25	0.00	97.41	0.00	98.39	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2132723717
95.37	0.02	94.82	0.01	92.80	0.00	94.55	0.09			94.26	0.01	97.41	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1093343077
95.39	0.02	94.82	0.00	92.85	0.05	94.55	0.00			94.27	0.02	97.41	0.00	98.43	0.04	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.103480079
95.40	0.01	94.82	0.00	92.94	0.08	94.55	0.00			94.27	0.00	97.41	0.00	98.43	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.177085999
95.41	0.01	94.82	0.00	92.94	0.00	94.62	0.07			94.27	0.00	97.41	0.00	98.43	0.00	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3952699909
95.43	0.01	94.82	0.00	92.94	0.00	94.62	0.00			94.27	0.00	97.41	0.00	98.50	0.07	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1119543862
95.44	0.01	94.82	0.00	92.99	0.06	94.62	0.00			94.27	0.00	97.41	0.00	98.51	0.01	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1072051330
95.45	0.01	94.82	0.01	93.05	0.06	94.62	0.00			94.27	0.00	97.41	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2883004316
95.46	0.01	94.82	0.00	93.06	0.01	94.68	0.06			94.27	0.00	97.41	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3251891067
95.47	0.01	94.82	0.00	93.10	0.04	94.68	0.00			94.29	0.02	97.41	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/83.xbar_stress_all.725680130
95.48	0.01	94.82	0.00	93.10	0.00	94.68	0.00			94.29	0.00	97.41	0.00	98.57	0.06	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2168821915
95.49	0.01	94.82	0.00	93.11	0.01	94.68	0.00			94.29	0.00	97.41	0.00	98.61	0.05	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2984907649
95.50	0.01	94.82	0.00	93.16	0.05	94.68	0.00			94.29	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.52470335
95.50	0.01	94.85	0.02	93.18	0.02	94.68	0.01			94.29	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.1719493311
95.51	0.01	94.87	0.03	93.19	0.01	94.69	0.01			94.31	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2018791530
95.52	0.01	94.90	0.03	93.20	0.01	94.69	0.01			94.32	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1527549345
95.53	0.01	94.91	0.02	93.20	0.01	94.70	0.01			94.34	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1951359469
95.54	0.01	94.91	0.00	93.25	0.05	94.70	0.00			94.34	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.1706848702
95.55	0.01	94.91	0.00	93.25	0.00	94.70	0.00			94.34	0.00	97.41	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1792256763
95.55	0.01	94.91	0.00	93.30	0.04	94.70	0.00			94.34	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2059210006
95.56	0.01	94.91	0.00	93.30	0.01	94.70	0.00			94.34	0.00	97.41	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1572265995
95.57	0.01	94.91	0.00	93.30	0.00	94.74	0.04			94.34	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4235142961
95.57	0.01	94.91	0.00	93.34	0.04	94.74	0.00			94.34	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.799108091
95.58	0.01	94.91	0.00	93.38	0.04	94.74	0.00			94.34	0.00	97.41	0.00	98.70	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1497865913
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95.69	0.01	94.96	0.00	93.64	0.00	94.94	0.00			94.36	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.50726930
95.69	0.01	94.96	0.00	93.64	0.00	94.94	0.00			94.36	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2347606150
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95.71	0.01	94.96	0.00	93.64	0.00	94.94	0.00			94.36	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3740864360
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95.80	0.01	94.96	0.00	93.64	0.00	94.94	0.00			94.36	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.2317660536
95.80	0.01	94.96	0.00	93.64	0.00	94.94	0.00			94.36	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599495647
95.80	0.01	94.96	0.00	93.64	0.00	94.94	0.00			94.36	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3103605092
95.81	0.01	94.96	0.00	93.64	0.00	94.94	0.00			94.36	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/88.chip_sw_all_escalation_resets.4196356339
95.81	0.01	94.96	0.00	93.64	0.00	94.94	0.00			94.36	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3398189757
95.81	0.01	94.96	0.00	93.65	0.01	94.94	0.00			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1423657494
95.81	0.01	94.96	0.00	93.66	0.01	94.94	0.00			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.2928236027
95.81	0.01	94.96	0.00	93.67	0.01	94.94	0.00			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1751881000
95.82	0.01	94.96	0.00	93.68	0.01	94.94	0.00			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3279241600
95.82	0.01	94.96	0.00	93.69	0.01	94.94	0.00			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.876000645
95.82	0.01	94.97	0.01	93.69	0.00	94.95	0.01			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/43.chip_sw_all_escalation_resets.948399053
95.82	0.01	94.97	0.00	93.69	0.00	94.96	0.01			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_init.1761487389
95.82	0.01	94.97	0.00	93.69	0.00	94.97	0.01			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2494185149
95.82	0.01	94.97	0.00	93.69	0.00	94.98	0.01			94.36	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2907554465
95.82	0.01	94.97	0.00	93.69	0.00	94.98	0.00			94.37	0.01	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.314774053
95.83	0.01	94.97	0.00	93.69	0.00	94.98	0.00			94.38	0.01	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.51457831
95.83	0.01	94.97	0.00	93.70	0.01	94.98	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1616759913
95.83	0.01	94.97	0.00	93.70	0.01	94.98	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/13.xbar_stress_all.2362603660
95.83	0.01	94.97	0.00	93.71	0.01	94.98	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2975132564
95.83	0.01	94.97	0.00	93.72	0.01	94.98	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4007570069
95.83	0.01	94.97	0.00	93.73	0.01	94.98	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_gpio.3699915877
95.83	0.01	94.97	0.01	93.73	0.01	94.98	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.451952004
95.83	0.01	94.97	0.00	93.73	0.00	94.98	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3103136880
95.84	0.01	94.97	0.00	93.73	0.00	94.99	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1023635280
95.84	0.01	94.97	0.00	93.73	0.00	95.00	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2283991812
95.84	0.01	94.97	0.00	93.73	0.00	95.01	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.914969325
95.84	0.01	94.97	0.00	93.73	0.00	95.01	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3691562103
95.84	0.01	94.97	0.00	93.73	0.00	95.01	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2700398393
95.84	0.01	94.97	0.00	93.73	0.00	95.02	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.871883048
95.84	0.01	94.97	0.00	93.73	0.00	95.02	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.206450566
95.84	0.01	94.97	0.00	93.73	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.3672791221
95.84	0.01	94.97	0.00	93.74	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.622990731
95.84	0.01	94.97	0.00	93.74	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.256829617
95.84	0.01	94.97	0.00	93.74	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3405656022
95.84	0.01	94.97	0.00	93.75	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/66.xbar_error_random.2569311933
95.85	0.01	94.97	0.00	93.75	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/68.xbar_error_random.1170040673
95.85	0.01	94.97	0.00	93.76	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.953652891
95.85	0.01	94.97	0.00	93.76	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1722820237
95.85	0.01	94.97	0.00	93.76	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2044314369
95.85	0.01	94.97	0.01	93.76	0.00	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1233769156
95.85	0.01	94.98	0.01	93.76	0.00	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2247322956
95.85	0.01	94.98	0.01	93.76	0.00	95.02	0.00			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2313555727
95.85	0.01	94.98	0.00	93.76	0.00	95.03	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.233982002
95.85	0.01	94.98	0.00	93.76	0.00	95.03	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1463604759
95.85	0.01	94.98	0.00	93.76	0.00	95.03	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.4064737400
95.85	0.01	94.98	0.00	93.76	0.00	95.03	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3414630455
95.85	0.01	94.98	0.00	93.76	0.00	95.04	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1636824619
95.85	0.01	94.98	0.00	93.76	0.00	95.04	0.01			94.38	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.203420154

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2380359379
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2637477312
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3605482272
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.986301929
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3975367037
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2921742054
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1536747868
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.785741988
/workspace/coverage/cover_reg_top/0.xbar_error_random.543536926
/workspace/coverage/cover_reg_top/0.xbar_random.2592087323
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.150728701
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.4234227560
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1065503231
/workspace/coverage/cover_reg_top/0.xbar_same_source.2331949113
/workspace/coverage/cover_reg_top/0.xbar_smoke.2876288764
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3983506440
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1230426389
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3597919195
/workspace/coverage/cover_reg_top/0.xbar_stress_all.598257616
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.494966825
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1495611125
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2816126149
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.362317987
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3753909489
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3632020371
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2041586724
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2788442085
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2028158622
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2371013397
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1399650651
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1255105707
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2958851480
/workspace/coverage/cover_reg_top/1.xbar_error_random.3498635267
/workspace/coverage/cover_reg_top/1.xbar_random.1952989337
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1847582213
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2496406638
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2256000863
/workspace/coverage/cover_reg_top/1.xbar_same_source.1391195000
/workspace/coverage/cover_reg_top/1.xbar_smoke.3521890221
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.363253851
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3639903506
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2974888343
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3061192580
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.978445069
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.767671726
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3765966327
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3228499158
/workspace/coverage/cover_reg_top/10.chip_csr_rw.4166195617
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.986455977
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2649008571
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3925311889
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1615976149
/workspace/coverage/cover_reg_top/10.xbar_error_random.2531210754
/workspace/coverage/cover_reg_top/10.xbar_random.3408835472
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1853223102
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1497273851
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2352171870
/workspace/coverage/cover_reg_top/10.xbar_same_source.493091396
/workspace/coverage/cover_reg_top/10.xbar_smoke.2006185905
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3214979288
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2066722820
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.4106562913
/workspace/coverage/cover_reg_top/10.xbar_stress_all.377076909
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.898506648
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4143031108
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3749554475
/workspace/coverage/cover_reg_top/11.chip_csr_rw.311458795
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2147851156
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3038864243
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.4138790768
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1624971927
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3015461916
/workspace/coverage/cover_reg_top/11.xbar_error_random.3823481637
/workspace/coverage/cover_reg_top/11.xbar_random.101729921
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.369858105
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2519345925
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3252538410
/workspace/coverage/cover_reg_top/11.xbar_same_source.4190758905
/workspace/coverage/cover_reg_top/11.xbar_smoke.2231796753
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4019484732
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2964601927
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1809936712
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2278815121
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.558105778
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3143081627
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1567656745
/workspace/coverage/cover_reg_top/12.chip_csr_rw.4173621381
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3657784124
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1168973736
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3421202855
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1434510267
/workspace/coverage/cover_reg_top/12.xbar_error_random.4066146633
/workspace/coverage/cover_reg_top/12.xbar_random.2543802299
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.675050130
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1903198364
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3941870174
/workspace/coverage/cover_reg_top/12.xbar_same_source.3779630677
/workspace/coverage/cover_reg_top/12.xbar_smoke.4167190138
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4118159049
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.974064190
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.165382736
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1443344632
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1596920005
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3392387378
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3656630454
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.68953511
/workspace/coverage/cover_reg_top/13.chip_csr_rw.880527470
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2588157974
/workspace/coverage/cover_reg_top/13.chip_tl_errors.1134502417
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.550848957
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.215478482
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.565704872
/workspace/coverage/cover_reg_top/13.xbar_error_random.1694084311
/workspace/coverage/cover_reg_top/13.xbar_random.509225724
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.4108786704
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.4092834213
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2889963539
/workspace/coverage/cover_reg_top/13.xbar_same_source.354307423
/workspace/coverage/cover_reg_top/13.xbar_smoke.3464168310
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3533898127
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1242166318
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3897944900
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1531275109
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4085845474
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2420855888
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3021288556
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/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1725574740
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3645798741
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3684961071
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2991866561
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3979632560
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3790111761
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3326129405
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3329341003
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.286022118
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.316853426
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2408474560
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2887725353
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2216019908
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.4080618729
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1289462370
/workspace/coverage/default/4.chip_tap_straps_dev.1323624552
/workspace/coverage/default/4.chip_tap_straps_prod.2834610579
/workspace/coverage/default/4.chip_tap_straps_rma.278343858
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2057103850
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3800397364
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1618286248
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2088273806
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3870253703
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2055128814
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1716930625
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3201370191
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2089564356
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2974191173
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3450196593
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3642745354
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2969258446
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2005542362
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2380884510
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2465501320
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3285305580
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1952815654
/workspace/coverage/default/50.chip_sw_all_escalation_resets.44003639
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1472411985
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3727746110
/workspace/coverage/default/53.chip_sw_all_escalation_resets.676941567
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.118489954
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.888012582
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153421343
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1665240132
/workspace/coverage/default/57.chip_sw_all_escalation_resets.426102297
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3801872220
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2206690648
/workspace/coverage/default/59.chip_sw_all_escalation_resets.777227421
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2671562712
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2841075042
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2056153289
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2257828110
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1117972745
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3905031221
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2534021368
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2465595008
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2362351411
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4214547569
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1055922324
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3097006920
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2803875504
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2206632042
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583668547
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1691593883
/workspace/coverage/default/69.chip_sw_all_escalation_resets.427731830
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2487746157
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3521317112
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4251670534
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040597339
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3064687666
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3865295697
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2488299225
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2874661761
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2484556887
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2542443246
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1720771734
/workspace/coverage/default/74.chip_sw_all_escalation_resets.4255432314
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1536144229
/workspace/coverage/default/75.chip_sw_all_escalation_resets.4142913656
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2727219722
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.273023414
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1160318755
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.923818379
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174138131
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3814642906
/workspace/coverage/default/8.chip_sw_all_escalation_resets.4103574822
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2199616590
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3998816961
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699865635
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2141947023
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1117968132
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1980403070
/workspace/coverage/default/83.chip_sw_all_escalation_resets.515800495
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1340549537
/workspace/coverage/default/84.chip_sw_all_escalation_resets.111612987
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4142390888
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3807991923
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1620193415
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3771334743
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.561665697
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2287852411
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3701956948
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.274311434
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3162466109
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122462095
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3395652428
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2800741187
/workspace/coverage/default/90.chip_sw_all_escalation_resets.206206986
/workspace/coverage/default/91.chip_sw_all_escalation_resets.4078183450
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3086038548
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3598824055
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2556647046
/workspace/coverage/default/95.chip_sw_all_escalation_resets.782820948
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3615229577
/workspace/coverage/default/98.chip_sw_all_escalation_resets.475121178
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1092676395
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.277838480
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3414011567
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2897640704
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3935415475
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.409312011
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3968553193
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3279824853
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3537965616

---

Total test records in report: 2831

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_edn_kat.525435905			Mar 17 03:54:26 PM PDT 24	Mar 17 04:05:15 PM PDT 24	3680280560 ps
T2	/workspace/coverage/default/1.chip_sival_flash_info_access.3126675881			Mar 17 03:51:33 PM PDT 24	Mar 17 03:56:03 PM PDT 24	2925604048 ps
T3	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.4005794114			Mar 17 03:48:55 PM PDT 24	Mar 17 03:59:22 PM PDT 24	4324573590 ps
T32	/workspace/coverage/default/48.chip_sw_all_escalation_resets.4059648525			Mar 17 04:15:51 PM PDT 24	Mar 17 04:26:24 PM PDT 24	5018641200 ps
T83	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2051788653			Mar 17 04:04:50 PM PDT 24	Mar 17 04:09:40 PM PDT 24	2896058940 ps
T39	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1077296666			Mar 17 03:55:27 PM PDT 24	Mar 17 04:22:49 PM PDT 24	6472835240 ps
T84	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1470277956			Mar 17 03:50:51 PM PDT 24	Mar 17 03:56:56 PM PDT 24	3430248880 ps
T49	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4160735342			Mar 17 04:15:20 PM PDT 24	Mar 17 04:24:42 PM PDT 24	4236304400 ps
T85	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1454732368			Mar 17 04:04:20 PM PDT 24	Mar 17 04:23:14 PM PDT 24	6155537596 ps
T4	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.216166953			Mar 17 03:53:30 PM PDT 24	Mar 17 04:24:22 PM PDT 24	8824338750 ps
T5	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2286373834			Mar 17 03:56:16 PM PDT 24	Mar 17 04:14:18 PM PDT 24	13876591060 ps
T57	/workspace/coverage/default/78.chip_sw_all_escalation_resets.2620864699			Mar 17 04:19:21 PM PDT 24	Mar 17 04:28:32 PM PDT 24	5371426812 ps
T58	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2314401234			Mar 17 03:54:42 PM PDT 24	Mar 17 04:19:52 PM PDT 24	9448722284 ps
T184	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1022477573			Mar 17 04:02:58 PM PDT 24	Mar 17 04:18:59 PM PDT 24	5268484580 ps
T170	/workspace/coverage/default/14.chip_sw_all_escalation_resets.405079489			Mar 17 04:12:40 PM PDT 24	Mar 17 04:23:16 PM PDT 24	5310384874 ps
T172	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1620193415			Mar 17 04:19:46 PM PDT 24	Mar 17 04:24:56 PM PDT 24	3529734164 ps
T62	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.4106754839			Mar 17 03:48:47 PM PDT 24	Mar 17 03:59:23 PM PDT 24	5640897440 ps
T103	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3371734024			Mar 17 03:53:38 PM PDT 24	Mar 17 04:51:39 PM PDT 24	17107941592 ps
T107	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3253428847			Mar 17 04:11:57 PM PDT 24	Mar 17 04:19:21 PM PDT 24	3373079000 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4263701464			Mar 17 04:05:53 PM PDT 24	Mar 17 04:13:25 PM PDT 24	6839802268 ps
T99	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2646196571			Mar 17 03:53:34 PM PDT 24	Mar 17 04:03:46 PM PDT 24	4729637308 ps
T63	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1050806563			Mar 17 03:57:11 PM PDT 24	Mar 17 04:07:13 PM PDT 24	5468990781 ps
T59	/workspace/coverage/default/1.chip_tap_straps_rma.2999134246			Mar 17 03:57:19 PM PDT 24	Mar 17 04:14:34 PM PDT 24	10090159216 ps
T65	/workspace/coverage/default/0.chip_tap_straps_dev.51457831			Mar 17 03:51:27 PM PDT 24	Mar 17 04:02:58 PM PDT 24	6894657830 ps
T100	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3251891067			Mar 17 03:54:28 PM PDT 24	Mar 17 04:00:27 PM PDT 24	6606735150 ps
T56	/workspace/coverage/default/2.rom_volatile_raw_unlock.1989493661			Mar 17 04:10:22 PM PDT 24	Mar 17 04:12:09 PM PDT 24	2237897865 ps
T6	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1256849555			Mar 17 03:56:10 PM PDT 24	Mar 17 04:40:08 PM PDT 24	11641659624 ps
T101	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1368758804			Mar 17 04:04:05 PM PDT 24	Mar 17 04:15:57 PM PDT 24	8355546500 ps
T102	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4213873095			Mar 17 04:06:31 PM PDT 24	Mar 17 04:18:02 PM PDT 24	6063421394 ps
T104	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.458125537			Mar 17 04:09:58 PM PDT 24	Mar 17 05:05:08 PM PDT 24	24117375069 ps
T415	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2778707367			Mar 17 03:55:37 PM PDT 24	Mar 17 04:02:21 PM PDT 24	4563298502 ps
T144	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.612466363			Mar 17 03:57:26 PM PDT 24	Mar 17 04:07:30 PM PDT 24	5076755750 ps
T145	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2197935144			Mar 17 03:55:32 PM PDT 24	Mar 17 04:05:38 PM PDT 24	3965684504 ps
T150	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.468257760			Mar 17 04:09:46 PM PDT 24	Mar 17 04:21:25 PM PDT 24	6443811656 ps
T108	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1706493137			Mar 17 03:51:09 PM PDT 24	Mar 17 03:56:18 PM PDT 24	2934590506 ps
T116	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2969258446			Mar 17 04:14:14 PM PDT 24	Mar 17 04:19:59 PM PDT 24	3605426340 ps
T130	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2542443246			Mar 17 04:17:12 PM PDT 24	Mar 17 04:24:46 PM PDT 24	5594276928 ps
T204	/workspace/coverage/default/50.chip_sw_all_escalation_resets.44003639			Mar 17 04:15:45 PM PDT 24	Mar 17 04:25:57 PM PDT 24	5276336160 ps
T17	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1918671228			Mar 17 03:58:53 PM PDT 24	Mar 17 04:06:29 PM PDT 24	7407851560 ps
T109	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1023635280			Mar 17 03:49:48 PM PDT 24	Mar 17 03:57:06 PM PDT 24	4488241707 ps
T906	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4134566591			Mar 17 04:04:53 PM PDT 24	Mar 17 04:08:21 PM PDT 24	2768482648 ps
T907	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3423340025			Mar 17 03:49:06 PM PDT 24	Mar 17 03:53:56 PM PDT 24	2496035800 ps
T803	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3740864360			Mar 17 04:12:41 PM PDT 24	Mar 17 04:18:51 PM PDT 24	3365029076 ps
T54	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2283991812			Mar 17 03:46:16 PM PDT 24	Mar 17 03:52:39 PM PDT 24	5874953732 ps
T129	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4022585983			Mar 17 03:54:44 PM PDT 24	Mar 17 04:04:20 PM PDT 24	4668169410 ps
T230	/workspace/coverage/default/2.chip_sw_plic_sw_irq.2548338177			Mar 17 04:06:10 PM PDT 24	Mar 17 04:10:51 PM PDT 24	2813310744 ps
T38	/workspace/coverage/default/2.rom_e2e_shutdown_output.631951286			Mar 17 04:13:14 PM PDT 24	Mar 17 04:57:43 PM PDT 24	22510278469 ps
T161	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1096185178			Mar 17 04:01:08 PM PDT 24	Mar 17 04:10:09 PM PDT 24	8864206640 ps
T121	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2868328834			Mar 17 04:05:07 PM PDT 24	Mar 17 04:37:13 PM PDT 24	18389901951 ps
T143	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3471986738			Mar 17 03:52:46 PM PDT 24	Mar 17 03:58:25 PM PDT 24	3804270819 ps
T125	/workspace/coverage/default/1.rom_volatile_raw_unlock.4069427296			Mar 17 04:01:00 PM PDT 24	Mar 17 04:02:49 PM PDT 24	2527608912 ps
T356	/workspace/coverage/default/2.rom_e2e_asm_init_prod.1243115742			Mar 17 04:13:50 PM PDT 24	Mar 17 04:44:04 PM PDT 24	8962588871 ps
T178	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.451952004			Mar 17 03:47:53 PM PDT 24	Mar 17 03:54:58 PM PDT 24	4097222784 ps
T79	/workspace/coverage/default/19.chip_sw_all_escalation_resets.2674610486			Mar 17 04:14:09 PM PDT 24	Mar 17 04:25:50 PM PDT 24	4917013452 ps
T90	/workspace/coverage/default/2.chip_sw_csrng_kat_test.451221428			Mar 17 04:07:18 PM PDT 24	Mar 17 04:10:47 PM PDT 24	3072860680 ps
T91	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3023798828			Mar 17 04:05:59 PM PDT 24	Mar 17 04:12:38 PM PDT 24	4816549208 ps
T92	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2656332542			Mar 17 03:52:11 PM PDT 24	Mar 17 04:05:49 PM PDT 24	5051735284 ps
T93	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.133553817			Mar 17 03:51:52 PM PDT 24	Mar 17 04:03:08 PM PDT 24	6432430936 ps
T55	/workspace/coverage/default/1.rom_raw_unlock.4246538070			Mar 17 04:02:04 PM PDT 24	Mar 17 04:35:24 PM PDT 24	15058876096 ps
T94	/workspace/coverage/default/5.chip_sw_all_escalation_resets.2465501320			Mar 17 04:11:56 PM PDT 24	Mar 17 04:26:09 PM PDT 24	6220341542 ps
T95	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1340549537			Mar 17 04:18:29 PM PDT 24	Mar 17 04:24:38 PM PDT 24	3445352010 ps
T96	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.830331754			Mar 17 03:50:52 PM PDT 24	Mar 17 03:59:08 PM PDT 24	5707414490 ps
T97	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1093397565			Mar 17 04:05:36 PM PDT 24	Mar 17 04:12:27 PM PDT 24	5342614388 ps
T60	/workspace/coverage/default/2.chip_tap_straps_testunlock0.1591585385			Mar 17 04:05:49 PM PDT 24	Mar 17 04:12:59 PM PDT 24	4084933785 ps
T237	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1239957146			Mar 17 04:02:17 PM PDT 24	Mar 17 04:04:18 PM PDT 24	2739215177 ps
T238	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2618771083			Mar 17 03:57:50 PM PDT 24	Mar 17 04:31:04 PM PDT 24	8744350350 ps
T239	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3629847510			Mar 17 03:50:53 PM PDT 24	Mar 17 03:53:39 PM PDT 24	2440093104 ps
T149	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2841276021			Mar 17 03:50:11 PM PDT 24	Mar 17 03:58:23 PM PDT 24	5554684552 ps
T294	/workspace/coverage/default/2.chip_sival_flash_info_access.356261149			Mar 17 04:02:01 PM PDT 24	Mar 17 04:07:21 PM PDT 24	2939599896 ps
T718	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.911188989			Mar 17 03:51:25 PM PDT 24	Mar 17 03:56:35 PM PDT 24	2672709668 ps
T413	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2141731767			Mar 17 04:07:11 PM PDT 24	Mar 17 04:11:38 PM PDT 24	3407685523 ps
T202	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.555186452			Mar 17 04:03:04 PM PDT 24	Mar 17 04:32:45 PM PDT 24	9935255416 ps
T908	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1535043569			Mar 17 04:03:53 PM PDT 24	Mar 17 04:22:46 PM PDT 24	8247492052 ps
T240	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4031020528			Mar 17 03:53:24 PM PDT 24	Mar 17 03:55:28 PM PDT 24	2330455725 ps
T684	/workspace/coverage/default/85.chip_sw_all_escalation_resets.3807991923			Mar 17 04:18:46 PM PDT 24	Mar 17 04:29:39 PM PDT 24	5530780712 ps
T357	/workspace/coverage/default/2.rom_e2e_smoke.1252623125			Mar 17 04:08:45 PM PDT 24	Mar 17 04:34:32 PM PDT 24	8692784732 ps
T203	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3895967929			Mar 17 04:03:15 PM PDT 24	Mar 17 04:17:14 PM PDT 24	14998239344 ps
T206	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.591164479			Mar 17 04:04:47 PM PDT 24	Mar 17 04:13:24 PM PDT 24	4115331786 ps
T40	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.673613397			Mar 17 03:47:07 PM PDT 24	Mar 17 03:52:19 PM PDT 24	3317225172 ps
T365	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2200627030			Mar 17 03:50:50 PM PDT 24	Mar 17 03:55:21 PM PDT 24	3199355048 ps
T366	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1197263774			Mar 17 03:50:13 PM PDT 24	Mar 17 03:54:00 PM PDT 24	2862345776 ps
T367	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3865295697			Mar 17 04:16:24 PM PDT 24	Mar 17 04:21:36 PM PDT 24	3826727394 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2112523026			Mar 17 03:58:31 PM PDT 24	Mar 17 04:20:47 PM PDT 24	17792490552 ps
T105	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3936599885			Mar 17 04:04:49 PM PDT 24	Mar 17 05:00:14 PM PDT 24	18787004553 ps
T368	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1048253648			Mar 17 04:05:53 PM PDT 24	Mar 17 04:10:49 PM PDT 24	3298406424 ps
T369	/workspace/coverage/default/91.chip_sw_all_escalation_resets.4078183450			Mar 17 04:19:14 PM PDT 24	Mar 17 04:26:58 PM PDT 24	5317141808 ps
T285	/workspace/coverage/default/1.chip_plic_all_irqs_20.1468881074			Mar 17 03:58:19 PM PDT 24	Mar 17 04:10:46 PM PDT 24	4522553240 ps
T305	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3720386480			Mar 17 03:52:27 PM PDT 24	Mar 17 04:27:28 PM PDT 24	19591110693 ps
T169	/workspace/coverage/default/2.chip_tap_straps_dev.2551762300			Mar 17 04:06:47 PM PDT 24	Mar 17 04:39:38 PM PDT 24	20117564695 ps
T909	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2358663293			Mar 17 04:07:13 PM PDT 24	Mar 17 04:17:57 PM PDT 24	4923830202 ps
T146	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3391289475			Mar 17 03:56:01 PM PDT 24	Mar 17 04:07:18 PM PDT 24	4551306170 ps
T33	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2060768524			Mar 17 04:01:31 PM PDT 24	Mar 17 04:05:51 PM PDT 24	3320722608 ps
T772	/workspace/coverage/default/74.chip_sw_all_escalation_resets.4255432314			Mar 17 04:17:27 PM PDT 24	Mar 17 04:27:32 PM PDT 24	5782166820 ps
T721	/workspace/coverage/default/1.chip_sw_hmac_smoketest.4062273275			Mar 17 04:01:01 PM PDT 24	Mar 17 04:07:36 PM PDT 24	3314464600 ps
T187	/workspace/coverage/default/4.chip_sw_uart_tx_rx.2408474560			Mar 17 04:09:58 PM PDT 24	Mar 17 04:24:28 PM PDT 24	5820598087 ps
T719	/workspace/coverage/default/1.chip_sw_aes_enc.2504651378			Mar 17 03:54:10 PM PDT 24	Mar 17 03:59:20 PM PDT 24	3044927728 ps
T910	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.923991869			Mar 17 04:04:03 PM PDT 24	Mar 17 04:14:11 PM PDT 24	5791605628 ps
T687	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3701956948			Mar 17 04:19:30 PM PDT 24	Mar 17 04:24:13 PM PDT 24	3649849166 ps
T911	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2837694812			Mar 17 03:56:28 PM PDT 24	Mar 17 04:02:07 PM PDT 24	6129231860 ps
T691	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3797700465			Mar 17 04:15:28 PM PDT 24	Mar 17 04:20:56 PM PDT 24	3425918730 ps
T232	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4228888756			Mar 17 04:10:42 PM PDT 24	Mar 17 04:15:08 PM PDT 24	3128863800 ps
T414	/workspace/coverage/default/2.chip_sw_kmac_entropy.978256459			Mar 17 04:02:12 PM PDT 24	Mar 17 04:06:04 PM PDT 24	2818737856 ps
T361	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1344955356			Mar 17 03:48:38 PM PDT 24	Mar 17 03:55:37 PM PDT 24	4515400052 ps
T13	/workspace/coverage/default/2.chip_sw_gpio.3930236895			Mar 17 04:01:54 PM PDT 24	Mar 17 04:11:16 PM PDT 24	3948627756 ps
T382	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2840523918			Mar 17 04:06:44 PM PDT 24	Mar 17 04:16:33 PM PDT 24	3991351540 ps
T126	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.408045949			Mar 17 04:08:39 PM PDT 24	Mar 17 04:31:40 PM PDT 24	25271668637 ps
T113	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3132129882			Mar 17 03:46:33 PM PDT 24	Mar 17 03:56:51 PM PDT 24	5336323944 ps
T383	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1245741451			Mar 17 03:51:14 PM PDT 24	Mar 17 04:07:25 PM PDT 24	7617750088 ps
T205	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.4251131875			Mar 17 04:12:47 PM PDT 24	Mar 17 04:19:50 PM PDT 24	4092460574 ps
T142	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.328907524			Mar 17 03:52:19 PM PDT 24	Mar 17 04:10:15 PM PDT 24	5674892730 ps
T223	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2834293644			Mar 17 03:48:31 PM PDT 24	Mar 17 04:11:40 PM PDT 24	8251401200 ps
T221	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3757123765			Mar 17 03:54:33 PM PDT 24	Mar 17 04:15:40 PM PDT 24	6399064364 ps
T912	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.4238237541			Mar 17 04:03:18 PM PDT 24	Mar 17 04:11:21 PM PDT 24	4970212252 ps
T241	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.850404598			Mar 17 03:47:05 PM PDT 24	Mar 17 03:48:59 PM PDT 24	2458263277 ps
T358	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.140493105			Mar 17 04:04:26 PM PDT 24	Mar 17 04:33:54 PM PDT 24	8551868180 ps
T147	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2694499595			Mar 17 03:50:29 PM PDT 24	Mar 17 04:36:23 PM PDT 24	10974128360 ps
T313	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3233986415			Mar 17 03:55:20 PM PDT 24	Mar 17 03:59:12 PM PDT 24	2284856870 ps
T185	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2041876435			Mar 17 03:46:00 PM PDT 24	Mar 17 03:58:15 PM PDT 24	4136706686 ps
T10	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1165608796			Mar 17 03:47:05 PM PDT 24	Mar 17 03:56:28 PM PDT 24	4570983527 ps
T913	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.145214832			Mar 17 03:51:32 PM PDT 24	Mar 17 04:00:16 PM PDT 24	3043154116 ps
T673	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1433254097			Mar 17 03:50:16 PM PDT 24	Mar 17 04:23:06 PM PDT 24	8515071476 ps
T14	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1036274437			Mar 17 04:01:55 PM PDT 24	Mar 17 04:38:43 PM PDT 24	14507618209 ps
T914	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1782990858			Mar 17 03:49:57 PM PDT 24	Mar 17 04:02:23 PM PDT 24	8267229560 ps
T724	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.4141149158			Mar 17 04:07:29 PM PDT 24	Mar 17 04:49:40 PM PDT 24	19902662436 ps
T696	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1094075684			Mar 17 04:14:38 PM PDT 24	Mar 17 04:20:50 PM PDT 24	3733929128 ps
T207	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4022125644			Mar 17 03:50:36 PM PDT 24	Mar 17 03:57:56 PM PDT 24	3777817684 ps
T179	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1883708222			Mar 17 04:02:27 PM PDT 24	Mar 17 04:16:56 PM PDT 24	4857175488 ps
T117	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3279241600			Mar 17 03:52:34 PM PDT 24	Mar 17 04:19:00 PM PDT 24	10283903660 ps
T915	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4159798656			Mar 17 03:56:13 PM PDT 24	Mar 17 03:59:39 PM PDT 24	2957999254 ps
T916	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1957511301			Mar 17 03:52:51 PM PDT 24	Mar 17 04:52:57 PM PDT 24	19165234554 ps
T61	/workspace/coverage/default/4.chip_tap_straps_testunlock0.2057103850			Mar 17 04:11:14 PM PDT 24	Mar 17 04:14:57 PM PDT 24	3458842796 ps
T917	/workspace/coverage/default/2.chip_sw_aes_smoketest.1327892578			Mar 17 04:08:27 PM PDT 24	Mar 17 04:14:41 PM PDT 24	2703825970 ps
T80	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2342417490			Mar 17 03:48:06 PM PDT 24	Mar 17 03:52:43 PM PDT 24	2650293474 ps
T686	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122462095			Mar 17 04:12:09 PM PDT 24	Mar 17 04:19:24 PM PDT 24	3541200638 ps
T183	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.560176574			Mar 17 03:47:38 PM PDT 24	Mar 17 04:09:42 PM PDT 24	9284133848 ps
T304	/workspace/coverage/default/0.chip_sw_pattgen_ios.3506145289			Mar 17 03:46:19 PM PDT 24	Mar 17 03:50:39 PM PDT 24	2905392200 ps
T918	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1527335903			Mar 17 03:55:51 PM PDT 24	Mar 17 04:03:43 PM PDT 24	6193831514 ps
T292	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.8586246			Mar 17 03:51:26 PM PDT 24	Mar 17 04:04:49 PM PDT 24	4828925866 ps
T72	/workspace/coverage/default/1.chip_jtag_csr_rw.199056147			Mar 17 03:49:31 PM PDT 24	Mar 17 04:30:43 PM PDT 24	18541105308 ps
T919	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2693220658			Mar 17 03:50:41 PM PDT 24	Mar 17 03:55:10 PM PDT 24	3578122188 ps
T692	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1472411985			Mar 17 04:15:08 PM PDT 24	Mar 17 04:20:33 PM PDT 24	3242724704 ps
T685	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2576637402			Mar 17 04:14:47 PM PDT 24	Mar 17 04:23:17 PM PDT 24	5346500792 ps
T920	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2594000084			Mar 17 03:58:27 PM PDT 24	Mar 17 04:32:09 PM PDT 24	8766401310 ps
T921	/workspace/coverage/default/2.chip_sw_aes_enc.1980965234			Mar 17 04:04:54 PM PDT 24	Mar 17 04:10:26 PM PDT 24	3175161544 ps
T922	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1036428122			Mar 17 03:51:28 PM PDT 24	Mar 17 03:56:27 PM PDT 24	3120853240 ps
T408	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1781609814			Mar 17 04:16:41 PM PDT 24	Mar 17 04:23:16 PM PDT 24	3272369688 ps
T755	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1725574740			Mar 17 04:13:57 PM PDT 24	Mar 17 04:20:05 PM PDT 24	4051430920 ps
T407	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4055337553			Mar 17 04:02:01 PM PDT 24	Mar 17 04:06:19 PM PDT 24	2499656528 ps
T676	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3103605092			Mar 17 04:18:44 PM PDT 24	Mar 17 04:23:31 PM PDT 24	3306705250 ps
T923	/workspace/coverage/default/2.chip_sw_aes_idle.3144144464			Mar 17 04:06:03 PM PDT 24	Mar 17 04:11:15 PM PDT 24	3154881970 ps
T400	/workspace/coverage/default/17.chip_sw_all_escalation_resets.3659036182			Mar 17 04:14:20 PM PDT 24	Mar 17 04:24:05 PM PDT 24	4950879472 ps
T404	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3942874591			Mar 17 03:57:39 PM PDT 24	Mar 17 04:07:39 PM PDT 24	5006629204 ps
T395	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1307940626			Mar 17 04:03:39 PM PDT 24	Mar 17 04:07:35 PM PDT 24	2820065608 ps
T405	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.310776315			Mar 17 04:04:03 PM PDT 24	Mar 17 04:11:07 PM PDT 24	3911392616 ps
T284	/workspace/coverage/default/0.chip_plic_all_irqs_0.2448665226			Mar 17 03:49:11 PM PDT 24	Mar 17 04:09:37 PM PDT 24	5778485000 ps
T188	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1920128576			Mar 17 03:46:44 PM PDT 24	Mar 17 04:41:13 PM PDT 24	22805423599 ps
T19	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2098220309			Mar 17 03:50:47 PM PDT 24	Mar 17 03:57:16 PM PDT 24	4543373386 ps
T196	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3742354482			Mar 17 03:56:16 PM PDT 24	Mar 17 04:25:41 PM PDT 24	8732523224 ps
T234	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2005542362			Mar 17 04:15:30 PM PDT 24	Mar 17 04:25:04 PM PDT 24	4884660686 ps
T406	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.394134291			Mar 17 03:54:48 PM PDT 24	Mar 17 04:01:50 PM PDT 24	3569934252 ps
T73	/workspace/coverage/default/2.rom_raw_unlock.3088566623			Mar 17 04:08:48 PM PDT 24	Mar 17 04:34:57 PM PDT 24	15030311477 ps
T924	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2028850549			Mar 17 03:47:53 PM PDT 24	Mar 17 03:52:28 PM PDT 24	3214266026 ps
T317	/workspace/coverage/default/60.chip_sw_all_escalation_resets.2056153289			Mar 17 04:16:04 PM PDT 24	Mar 17 04:25:52 PM PDT 24	5212650518 ps
T131	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.903807279			Mar 17 03:58:55 PM PDT 24	Mar 17 04:01:31 PM PDT 24	4025896620 ps
T925	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.965506824			Mar 17 03:48:45 PM PDT 24	Mar 17 03:57:28 PM PDT 24	3709978664 ps
T350	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2742707723			Mar 17 04:06:30 PM PDT 24	Mar 17 04:22:56 PM PDT 24	9244245446 ps
T20	/workspace/coverage/default/0.chip_sw_usbdev_config_host.150870309			Mar 17 03:46:51 PM PDT 24	Mar 17 04:22:28 PM PDT 24	8163482176 ps
T64	/workspace/coverage/default/0.chip_tap_straps_testunlock0.4184873353			Mar 17 03:51:36 PM PDT 24	Mar 17 04:09:09 PM PDT 24	9828648329 ps
T110	/workspace/coverage/default/0.chip_plic_all_irqs_10.2499890271			Mar 17 03:50:33 PM PDT 24	Mar 17 04:01:17 PM PDT 24	3630395214 ps
T339	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3905031221			Mar 17 04:16:15 PM PDT 24	Mar 17 04:27:07 PM PDT 24	5041383048 ps
T343	/workspace/coverage/default/2.chip_tap_straps_prod.122238551			Mar 17 04:06:57 PM PDT 24	Mar 17 04:09:18 PM PDT 24	2313040566 ps
T344	/workspace/coverage/default/2.chip_sw_example_rom.3556537464			Mar 17 04:00:13 PM PDT 24	Mar 17 04:02:22 PM PDT 24	2814814184 ps
T345	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.590489085			Mar 17 04:03:41 PM PDT 24	Mar 17 04:08:12 PM PDT 24	2470168436 ps
T346	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3777932363			Mar 17 03:45:45 PM PDT 24	Mar 17 04:02:20 PM PDT 24	5717781478 ps
T347	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.482145994			Mar 17 04:14:27 PM PDT 24	Mar 17 04:21:59 PM PDT 24	4002880438 ps
T233	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.359724067			Mar 17 04:05:17 PM PDT 24	Mar 17 04:11:30 PM PDT 24	2369604162 ps
T348	/workspace/coverage/default/38.chip_sw_all_escalation_resets.2991866561			Mar 17 04:15:00 PM PDT 24	Mar 17 04:27:37 PM PDT 24	6404026650 ps
T242	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.471577692			Mar 17 03:54:05 PM PDT 24	Mar 17 04:27:17 PM PDT 24	9364064985 ps
T349	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3363579471			Mar 17 03:54:06 PM PDT 24	Mar 17 04:24:35 PM PDT 24	8874273467 ps
T694	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1631628936			Mar 17 04:13:29 PM PDT 24	Mar 17 04:22:53 PM PDT 24	5671781802 ps
T243	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3287780520			Mar 17 04:05:50 PM PDT 24	Mar 17 04:14:34 PM PDT 24	8678278315 ps
T333	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.229052921			Mar 17 03:53:51 PM PDT 24	Mar 17 04:38:22 PM PDT 24	12283145668 ps
T760	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1618286248			Mar 17 04:14:12 PM PDT 24	Mar 17 04:23:22 PM PDT 24	5780617532 ps
T190	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3952699909			Mar 17 04:11:58 PM PDT 24	Mar 17 04:20:57 PM PDT 24	5007778714 ps
T926	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2899063885			Mar 17 04:04:42 PM PDT 24	Mar 17 04:09:07 PM PDT 24	2982702550 ps
T682	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1205697634			Mar 17 03:51:43 PM PDT 24	Mar 17 03:53:32 PM PDT 24	2625745555 ps
T927	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2010534253			Mar 17 03:51:20 PM PDT 24	Mar 17 04:00:10 PM PDT 24	5434322760 ps
T132	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3534766636			Mar 17 03:45:50 PM PDT 24	Mar 17 03:47:35 PM PDT 24	3309939444 ps
T928	/workspace/coverage/default/0.rom_e2e_asm_init_dev.416641930			Mar 17 03:57:33 PM PDT 24	Mar 17 04:31:44 PM PDT 24	8772485890 ps
T805	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.133714835			Mar 17 04:14:27 PM PDT 24	Mar 17 04:20:59 PM PDT 24	3734715656 ps
T929	/workspace/coverage/default/4.chip_tap_straps_rma.278343858			Mar 17 04:10:23 PM PDT 24	Mar 17 04:13:29 PM PDT 24	2599405556 ps
T930	/workspace/coverage/default/0.rom_keymgr_functest.3290442185			Mar 17 03:51:17 PM PDT 24	Mar 17 03:59:22 PM PDT 24	5088141236 ps
T244	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3823263146			Mar 17 03:55:17 PM PDT 24	Mar 17 04:24:22 PM PDT 24	9322800798 ps
T111	/workspace/coverage/default/1.chip_plic_all_irqs_10.52470335			Mar 17 03:57:37 PM PDT 24	Mar 17 04:05:37 PM PDT 24	3873386650 ps
T725	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2743726676			Mar 17 03:48:26 PM PDT 24	Mar 17 04:29:18 PM PDT 24	25829372536 ps
T798	/workspace/coverage/default/29.chip_sw_all_escalation_resets.775139922			Mar 17 04:12:19 PM PDT 24	Mar 17 04:20:12 PM PDT 24	4262635344 ps
T164	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3504231209			Mar 17 04:02:23 PM PDT 24	Mar 17 07:11:14 PM PDT 24	63619096528 ps
T931	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1984615558			Mar 17 04:01:43 PM PDT 24	Mar 17 04:05:16 PM PDT 24	2055493112 ps
T174	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1244300719			Mar 17 03:48:05 PM PDT 24	Mar 17 03:54:03 PM PDT 24	2891571648 ps
T762	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1659865481			Mar 17 03:52:08 PM PDT 24	Mar 17 04:15:39 PM PDT 24	9294630040 ps
T683	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3801713028			Mar 17 04:03:06 PM PDT 24	Mar 17 04:05:05 PM PDT 24	1928884774 ps
T11	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3945281508			Mar 17 04:04:34 PM PDT 24	Mar 17 04:13:47 PM PDT 24	5097104558 ps
T134	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.18909980			Mar 17 03:49:57 PM PDT 24	Mar 17 04:00:18 PM PDT 24	4969038428 ps
T262	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614410850			Mar 17 04:13:32 PM PDT 24	Mar 17 04:20:20 PM PDT 24	3818214952 ps
T153	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.286022118			Mar 17 04:11:55 PM PDT 24	Mar 17 04:23:54 PM PDT 24	8192922898 ps
T148	/workspace/coverage/default/0.chip_sw_edn_auto_mode.4064737400			Mar 17 03:47:57 PM PDT 24	Mar 17 04:07:18 PM PDT 24	4649499348 ps
T133	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.63410641			Mar 17 03:47:07 PM PDT 24	Mar 17 03:49:19 PM PDT 24	3363451896 ps
T263	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2525968257			Mar 17 03:58:12 PM PDT 24	Mar 17 04:01:56 PM PDT 24	3159555626 ps
T264	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1460242097			Mar 17 04:11:45 PM PDT 24	Mar 17 04:21:34 PM PDT 24	3506655112 ps
T265	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2380884510			Mar 17 04:11:31 PM PDT 24	Mar 17 04:18:44 PM PDT 24	4307133336 ps
T266	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2061710258			Mar 17 04:13:35 PM PDT 24	Mar 17 04:23:41 PM PDT 24	5990182454 ps
T81	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.897968792			Mar 17 04:05:08 PM PDT 24	Mar 17 07:06:18 PM PDT 24	255506257232 ps
T693	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2775807884			Mar 17 04:20:44 PM PDT 24	Mar 17 04:25:57 PM PDT 24	3396009200 ps
T224	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2552380861			Mar 17 04:03:55 PM PDT 24	Mar 17 04:34:50 PM PDT 24	12030989690 ps
T12	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.963421450			Mar 17 03:47:27 PM PDT 24	Mar 17 03:51:34 PM PDT 24	3265922500 ps
T932	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1648194303			Mar 17 04:04:49 PM PDT 24	Mar 17 05:06:24 PM PDT 24	17303524632 ps
T24	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2410432026			Mar 17 03:46:06 PM PDT 24	Mar 17 05:34:56 PM PDT 24	31586332300 ps
T25	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2959891680			Mar 17 03:52:07 PM PDT 24	Mar 17 04:03:59 PM PDT 24	3563287240 ps
T674	/workspace/coverage/default/18.chip_sw_all_escalation_resets.4005810877			Mar 17 04:11:54 PM PDT 24	Mar 17 04:21:26 PM PDT 24	4621304688 ps
T226	/workspace/coverage/default/6.chip_sw_all_escalation_resets.486952495			Mar 17 04:12:18 PM PDT 24	Mar 17 04:21:34 PM PDT 24	5183565328 ps
T933	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2640369760			Mar 17 03:56:12 PM PDT 24	Mar 17 04:05:07 PM PDT 24	5431492066 ps
T222	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1685334472			Mar 17 04:05:17 PM PDT 24	Mar 17 04:24:13 PM PDT 24	5410739232 ps
T723	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3366656286			Mar 17 03:51:40 PM PDT 24	Mar 17 03:55:22 PM PDT 24	3023678140 ps
T796	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3097006920			Mar 17 04:18:09 PM PDT 24	Mar 17 04:23:44 PM PDT 24	3916463750 ps
T934	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3549877928			Mar 17 03:57:55 PM PDT 24	Mar 17 04:19:06 PM PDT 24	7685122544 ps
T396	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.647513988			Mar 17 03:56:17 PM PDT 24	Mar 17 04:01:14 PM PDT 24	3400143096 ps
T180	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2027469548			Mar 17 04:11:08 PM PDT 24	Mar 17 04:25:44 PM PDT 24	5212550594 ps
T794	/workspace/coverage/default/75.chip_sw_all_escalation_resets.4142913656			Mar 17 04:17:39 PM PDT 24	Mar 17 04:27:56 PM PDT 24	5318067466 ps
T935	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2564848035			Mar 17 03:50:17 PM PDT 24	Mar 17 03:55:58 PM PDT 24	2951456070 ps
T15	/workspace/coverage/default/2.chip_sw_gpio_smoketest.1543278118			Mar 17 04:09:58 PM PDT 24	Mar 17 04:14:57 PM PDT 24	2816187311 ps
T112	/workspace/coverage/default/2.chip_plic_all_irqs_10.895751414			Mar 17 04:06:30 PM PDT 24	Mar 17 04:14:58 PM PDT 24	3627564328 ps
T936	/workspace/coverage/default/0.chip_sw_example_manufacturer.3836061835			Mar 17 03:45:42 PM PDT 24	Mar 17 03:49:08 PM PDT 24	2269734000 ps
T937	/workspace/coverage/default/2.rom_e2e_asm_init_dev.2680271462			Mar 17 04:13:02 PM PDT 24	Mar 17 04:37:05 PM PDT 24	8823768426 ps
T517	/workspace/coverage/default/52.chip_sw_all_escalation_resets.3727746110			Mar 17 04:14:45 PM PDT 24	Mar 17 04:27:04 PM PDT 24	5871765144 ps
T695	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4142390888			Mar 17 04:19:11 PM PDT 24	Mar 17 04:26:41 PM PDT 24	4094454378 ps
T757	/workspace/coverage/default/39.chip_sw_all_escalation_resets.3979632560			Mar 17 04:17:08 PM PDT 24	Mar 17 04:27:29 PM PDT 24	5361041960 ps
T819	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2055128814			Mar 17 04:14:33 PM PDT 24	Mar 17 04:23:28 PM PDT 24	4748912440 ps
T518	/workspace/coverage/default/90.chip_sw_all_escalation_resets.206206986			Mar 17 04:21:07 PM PDT 24	Mar 17 04:30:01 PM PDT 24	5166503600 ps
T766	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.271983865			Mar 17 04:12:16 PM PDT 24	Mar 17 04:16:35 PM PDT 24	3068375000 ps
T938	/workspace/coverage/default/1.chip_sw_edn_sw_mode.4124158938			Mar 17 03:53:29 PM PDT 24	Mar 17 04:15:38 PM PDT 24	5992771064 ps
T939	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2240506140			Mar 17 04:07:32 PM PDT 24	Mar 17 04:12:29 PM PDT 24	2583571853 ps
T940	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1005182030			Mar 17 04:03:59 PM PDT 24	Mar 17 04:26:58 PM PDT 24	7252128460 ps
T677	/workspace/coverage/default/45.chip_sw_all_escalation_resets.1389741053			Mar 17 04:14:56 PM PDT 24	Mar 17 04:25:32 PM PDT 24	5763719130 ps
T941	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2164402106			Mar 17 04:09:10 PM PDT 24	Mar 17 04:11:30 PM PDT 24	2790253330 ps
T127	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2754096843			Mar 17 03:54:57 PM PDT 24	Mar 17 05:25:27 PM PDT 24	49924151997 ps
T225	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1280362356			Mar 17 03:53:02 PM PDT 24	Mar 17 04:01:17 PM PDT 24	4099312136 ps
T137	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.150300774			Mar 17 03:58:30 PM PDT 24	Mar 17 04:03:15 PM PDT 24	2832094834 ps
T275	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.718118735			Mar 17 03:52:53 PM PDT 24	Mar 17 04:08:26 PM PDT 24	5545171616 ps
T276	/workspace/coverage/default/2.chip_sw_example_manufacturer.2231270242			Mar 17 04:01:40 PM PDT 24	Mar 17 04:04:45 PM PDT 24	2819935142 ps
T135	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2927106442			Mar 17 03:55:07 PM PDT 24	Mar 17 04:03:03 PM PDT 24	4389887740 ps