Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135750	1			T69	78		T70	7		T76	8
values[2]	9321	1			T69	7		T70	1		T76	1
values[3]	3787	1			T393	1		T443	1		T587	29
values[4]	2118	1			T587	9		T392	15		T841	1
values[5]	1261	1			T587	10		T392	13		T841	1
values[6]	878	1			T587	8		T392	9		T841	1
values[7]	611	1			T587	2		T392	15		T841	1
values[8]	489	1			T587	1		T392	14		T841	1
values[9]	426	1			T392	8		T841	1		T739	15
values[10]	379	1			T392	17		T841	1		T739	20
values[11]	303	1			T392	15		T841	1		T739	22
values[12]	269	1			T392	10		T841	1		T739	15
values[13]	328	1			T392	11		T841	1		T739	12
values[14]	267	1			T392	14		T841	1		T739	20
values[15]	277	1			T392	26		T841	1		T739	23
values[16]	242	1			T392	18		T841	1		T739	4
values[17]	267	1			T392	14		T841	1		T477	7
values[18]	247	1			T392	11		T841	1		T477	4
values[19]	239	1			T392	12		T841	1		T477	6
values[20]	296	1			T392	9		T841	1		T477	8
values[21]	271	1			T392	19		T841	1		T477	11
values[22]	310	1			T392	13		T841	1		T477	9
values[23]	254	1			T392	14		T841	1		T477	7
values[24]	266	1			T392	19		T841	1		T477	2
values[25]	262	1			T392	9		T841	1		T477	6
values[26]	249	1			T392	11		T841	1		T477	6
values[27]	227	1			T392	18		T841	1		T477	8
values[28]	246	1			T392	10		T841	1		T477	8
values[29]	231	1			T392	14		T841	1		T477	3
values[30]	269	1			T392	19		T841	1		T477	1
values[31]	232	1			T392	17		T841	1		T831	8
values[32]	274	1			T392	23		T841	1		T831	5
values[33]	257	1			T392	8		T841	1		T831	4
values[34]	204	1			T392	10		T841	1		T831	9
values[35]	213	1			T392	9		T841	1		T831	5
values[36]	227	1			T392	19		T841	1		T831	4
values[37]	259	1			T392	12		T841	1		T831	7
values[38]	212	1			T392	11		T841	1		T831	8
values[39]	235	1			T392	16		T841	1		T831	10
values[40]	247	1			T392	30		T841	1		T831	7
values[41]	217	1			T392	7		T841	1		T831	19
values[42]	195	1			T392	13		T841	1		T831	4
values[43]	193	1			T392	16		T841	1		T831	5
values[44]	235	1			T392	20		T841	1		T831	4
values[45]	208	1			T392	13		T841	1		T831	12
values[46]	251	1			T392	19		T841	1		T831	4
values[47]	240	1			T392	15		T841	1		T831	4
values[48]	222	1			T392	11		T841	1		T831	3
values[49]	262	1			T392	10		T841	1		T831	12
values[50]	215	1			T392	16		T841	1		T831	10
values[51]	210	1			T392	11		T841	1		T831	10
values[52]	238	1			T392	16		T841	1		T831	4
values[53]	260	1			T392	16		T841	1		T831	10
values[54]	216	1			T392	9		T841	1		T831	5
values[55]	224	1			T392	14		T841	1		T831	5
values[56]	183	1			T392	18		T841	1		T831	5
values[57]	198	1			T392	23		T841	1		T831	3
values[58]	178	1			T392	12		T841	1		T831	11
values[59]	182	1			T392	9		T841	1		T831	11
values[60]	179	1			T392	12		T841	1		T831	2
values[61]	180	1			T392	3		T841	1		T831	5
values[62]	144	1			T392	6		T841	1		T831	4
values[63]	146	1			T392	5		T841	1		T831	6
values[64]	128	1			T392	9		T841	1		T831	6
values[65]	116	1			T392	16		T841	1		T831	7
values[66]	120	1			T841	1		T831	1		T861	2
values[67]	127	1			T841	1		T861	1		T874	1
values[68]	131	1			T841	1		T861	7		T874	1
values[69]	137	1			T841	2		T861	3		T874	1
values[70]	128	1			T841	1		T861	2		T874	1
values[71]	95	1			T841	1		T861	3		T874	1
values[72]	81	1			T841	1		T861	2		T874	1
values[73]	93	1			T841	1		T861	3		T874	1
values[74]	87	1			T841	1		T861	3		T874	1
values[75]	57	1			T841	1		T861	1		T874	1
values[76]	63	1			T841	1		T861	1		T874	1
values[77]	74	1			T841	1		T861	1		T874	1
values[78]	80	1			T841	1		T861	2		T874	1
values[79]	69	1			T841	1		T874	1		T875	1
values[80]	63	1			T841	1		T874	1		T875	1
values[81]	69	1			T841	1		T874	1		T875	1
values[82]	62	1			T841	1		T874	1		T875	1
values[83]	78	1			T841	1		T874	1		T875	1
values[84]	95	1			T841	1		T874	1		T875	1
values[85]	101	1			T841	1		T874	1		T875	1
values[86]	85	1			T841	1		T874	1		T875	1
values[87]	80	1			T841	1		T874	1		T875	1
values[88]	97	1			T841	1		T874	1		T875	2
values[89]	101	1			T841	1		T874	1		T875	1
values[90]	100	1			T841	1		T874	1		T875	1
values[91]	136	1			T841	1		T874	1		T875	1
values[92]	103	1			T841	1		T874	1		T875	1
values[93]	94	1			T841	1		T874	1		T875	1
values[94]	68	1			T841	1		T874	1		T875	1
values[95]	76	1			T841	1		T874	1		T875	1
values[96]	67	1			T841	1		T874	1		T875	1
values[97]	74	1			T841	1		T874	1		T875	1
values[98]	86	1			T841	1		T874	1		T875	1
values[99]	84	1			T841	1		T874	2		T875	1
values[100]	67	1			T841	1		T874	1		T875	1
values[101]	77	1			T841	1		T874	1		T875	1
values[102]	87	1			T841	1		T874	1		T875	3
values[103]	69	1			T841	1		T874	1		T875	6
values[104]	61	1			T841	1		T874	1		T875	3
values[105]	74	1			T841	1		T874	1		T875	2
values[106]	77	1			T841	2		T874	1		T875	2
values[107]	60	1			T841	1		T874	1		T875	1
values[108]	80	1			T841	1		T874	1		T875	1
values[109]	77	1			T841	1		T874	1		T875	3
values[110]	72	1			T841	1		T874	1		T875	1
values[111]	73	1			T841	1		T874	1		T875	1
values[112]	55	1			T841	1		T874	1		T875	2
values[113]	56	1			T841	1		T874	1		T875	2
values[114]	75	1			T841	4		T874	1		T875	1
values[115]	80	1			T841	1		T874	1		T875	2
values[116]	77	1			T841	3		T874	1		T875	1
values[117]	75	1			T841	1		T874	1		T875	5
values[118]	45	1			T841	1		T874	1		T875	1
values[119]	53	1			T841	1		T874	1		T875	1
values[120]	74	1			T841	1		T874	1		T875	2
values[121]	45	1			T841	1		T874	1		T875	1
values[122]	56	1			T841	1		T874	1		T875	2
values[123]	71	1			T841	1		T874	1		T875	2
values[124]	63	1			T841	2		T874	1		T875	1
values[125]	72	1			T841	1		T874	2		T875	1
values[126]	121	1			T841	1		T874	3		T875	1
values[127]	655	1			T841	38		T874	30		T875	33
values[128]	4941	1			T841	414		T874	303		T875	260