Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	133649	1			T69	94		T70	5		T76	3
values[2]	9387	1			T69	5		T76	1		T78	2
values[3]	3952	1			T522	1		T521	23		T393	1
values[4]	2443	1			T522	1		T521	19		T443	12
values[5]	1644	1			T522	1		T521	21		T443	1
values[6]	1356	1			T522	1		T521	23		T537	10
values[7]	935	1			T522	1		T521	9		T537	3
values[8]	707	1			T522	1		T521	8		T537	13
values[9]	567	1			T522	1		T521	10		T537	9
values[10]	492	1			T522	1		T521	10		T537	8
values[11]	492	1			T522	1		T521	8		T537	11
values[12]	432	1			T522	1		T521	12		T537	6
values[13]	458	1			T522	1		T521	9		T537	6
values[14]	422	1			T522	1		T521	6		T537	12
values[15]	404	1			T522	1		T521	4		T537	3
values[16]	386	1			T522	1		T521	4		T537	6
values[17]	392	1			T522	1		T521	2		T537	6
values[18]	406	1			T522	1		T521	1		T537	7
values[19]	416	1			T522	1		T521	1		T537	7
values[20]	428	1			T522	1		T537	13		T667	7
values[21]	363	1			T522	1		T537	5		T667	7
values[22]	435	1			T522	1		T537	6		T667	16
values[23]	364	1			T522	1		T537	4		T667	7
values[24]	394	1			T522	1		T537	7		T667	5
values[25]	369	1			T522	1		T537	8		T667	5
values[26]	381	1			T522	1		T537	15		T667	9
values[27]	372	1			T522	1		T537	6		T667	15
values[28]	365	1			T522	1		T537	6		T667	3
values[29]	413	1			T522	1		T537	9		T667	10
values[30]	429	1			T522	1		T537	6		T667	6
values[31]	375	1			T522	1		T537	13		T667	7
values[32]	389	1			T522	1		T537	11		T667	3
values[33]	347	1			T522	1		T537	14		T667	6
values[34]	408	1			T522	1		T537	4		T667	11
values[35]	432	1			T522	1		T537	5		T667	11
values[36]	406	1			T522	1		T537	6		T667	11
values[37]	386	1			T522	1		T537	8		T667	8
values[38]	412	1			T522	1		T537	5		T667	6
values[39]	353	1			T522	1		T537	7		T667	5
values[40]	362	1			T522	1		T537	3		T667	3
values[41]	374	1			T522	1		T537	3		T667	6
values[42]	293	1			T522	1		T537	8		T667	7
values[43]	317	1			T522	1		T537	4		T667	4
values[44]	320	1			T522	1		T537	4		T667	8
values[45]	358	1			T522	1		T537	5		T667	5
values[46]	331	1			T522	1		T537	3		T667	3
values[47]	315	1			T522	1		T537	7		T667	8
values[48]	321	1			T522	1		T537	4		T667	18
values[49]	321	1			T522	1		T537	3		T667	9
values[50]	331	1			T522	1		T537	10		T667	10
values[51]	278	1			T522	1		T537	8		T667	8
values[52]	275	1			T522	1		T537	10		T667	2
values[53]	341	1			T522	1		T537	7		T667	4
values[54]	315	1			T522	1		T537	6		T667	4
values[55]	340	1			T522	1		T537	5		T667	7
values[56]	244	1			T522	1		T537	12		T667	3
values[57]	236	1			T522	1		T537	5		T667	5
values[58]	288	1			T522	1		T537	8		T667	3
values[59]	290	1			T522	1		T537	14		T667	4
values[60]	244	1			T522	1		T537	13		T667	7
values[61]	249	1			T522	1		T537	9		T667	12
values[62]	196	1			T522	1		T537	3		T667	6
values[63]	198	1			T522	1		T537	10		T667	14
values[64]	212	1			T522	1		T537	11		T667	2
values[65]	256	1			T522	1		T537	13		T428	20
values[66]	175	1			T522	1		T537	6		T428	7
values[67]	178	1			T522	1		T537	3		T830	4
values[68]	182	1			T522	1		T842	1		T866	9
values[69]	181	1			T522	1		T842	1		T866	9
values[70]	150	1			T522	2		T842	1		T866	9
values[71]	165	1			T522	1		T842	1		T866	6
values[72]	109	1			T522	1		T842	1		T866	13
values[73]	135	1			T522	1		T842	1		T866	11
values[74]	101	1			T522	1		T842	1		T866	2
values[75]	115	1			T522	1		T842	1		T850	1
values[76]	92	1			T522	1		T842	1		T850	10
values[77]	69	1			T522	1		T842	1		T850	13
values[78]	58	1			T522	1		T842	2		T850	3
values[79]	59	1			T522	1		T842	1		T850	2
values[80]	40	1			T522	1		T842	1		T850	2
values[81]	42	1			T522	1		T842	1		T850	5
values[82]	54	1			T522	1		T842	1		T850	2
values[83]	48	1			T522	1		T842	1		T850	4
values[84]	54	1			T522	1		T842	1		T850	6
values[85]	66	1			T522	1		T842	1		T850	7
values[86]	46	1			T522	1		T842	1		T850	5
values[87]	65	1			T522	1		T842	1		T850	1
values[88]	61	1			T522	1		T842	1		T850	1
values[89]	76	1			T522	1		T842	1		T850	4
values[90]	69	1			T522	1		T842	1		T850	2
values[91]	88	1			T522	1		T842	1		T850	7
values[92]	75	1			T522	1		T842	1		T850	7
values[93]	59	1			T522	1		T842	1		T850	4
values[94]	49	1			T522	1		T842	1		T850	4
values[95]	57	1			T522	1		T842	1		T850	4
values[96]	65	1			T522	1		T842	1		T850	6
values[97]	58	1			T522	1		T842	1		T850	7
values[98]	56	1			T522	1		T842	1		T850	8
values[99]	59	1			T522	1		T842	1		T850	8
values[100]	53	1			T522	1		T842	1		T850	2
values[101]	57	1			T522	1		T842	1		T850	3
values[102]	58	1			T522	1		T842	1		T850	2
values[103]	48	1			T522	1		T842	1		T850	2
values[104]	68	1			T522	1		T842	1		T850	5
values[105]	51	1			T522	1		T842	1		T850	4
values[106]	58	1			T522	1		T842	1		T850	5
values[107]	58	1			T522	1		T842	4		T850	5
values[108]	59	1			T522	1		T842	1		T850	6
values[109]	43	1			T522	1		T842	1		T850	5
values[110]	52	1			T522	1		T842	2		T850	1
values[111]	58	1			T522	1		T842	1		T850	4
values[112]	75	1			T522	1		T842	2		T850	4
values[113]	75	1			T522	1		T842	1		T850	7
values[114]	63	1			T522	1		T842	2		T850	4
values[115]	59	1			T522	1		T842	1		T850	1
values[116]	69	1			T522	1		T842	2		T850	6
values[117]	59	1			T522	1		T842	1		T850	4
values[118]	58	1			T522	1		T842	2		T850	8
values[119]	66	1			T522	1		T842	4		T850	3
values[120]	55	1			T522	1		T842	2		T850	5
values[121]	57	1			T522	1		T842	1		T850	3
values[122]	61	1			T522	1		T842	2		T850	2
values[123]	59	1			T522	1		T842	2		T850	4
values[124]	69	1			T522	4		T842	1		T850	9
values[125]	75	1			T522	1		T842	1		T850	19
values[126]	141	1			T522	2		T842	3		T850	38
values[127]	594	1			T522	44		T842	22		T850	54
values[128]	4087	1			T522	378		T842	291		T850	32