Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136980	1			T69	89		T70	6		T76	9
values[2]	10647	1			T69	2		T463	4		T417	2
values[3]	5108	1			T522	2		T521	64		T587	1
values[4]	3047	1			T522	2		T521	64		T428	12
values[5]	1833	1			T522	2		T521	37		T428	7
values[6]	1365	1			T522	2		T521	47		T428	5
values[7]	1023	1			T522	2		T521	41		T428	7
values[8]	714	1			T522	2		T521	22		T428	5
values[9]	635	1			T522	2		T521	6		T428	11
values[10]	506	1			T522	2		T428	4		T739	10
values[11]	365	1			T522	2		T428	14		T739	6
values[12]	339	1			T522	2		T428	5		T739	4
values[13]	293	1			T522	2		T428	5		T832	1
values[14]	264	1			T522	2		T428	4		T832	1
values[15]	249	1			T522	2		T428	3		T832	1
values[16]	263	1			T522	2		T428	22		T832	1
values[17]	232	1			T522	2		T428	7		T832	2
values[18]	269	1			T522	2		T428	5		T832	1
values[19]	255	1			T522	2		T428	4		T832	1
values[20]	305	1			T522	2		T428	8		T832	1
values[21]	239	1			T522	2		T428	8		T832	1
values[22]	293	1			T522	2		T428	6		T832	1
values[23]	262	1			T522	2		T428	4		T832	1
values[24]	206	1			T522	2		T428	11		T832	1
values[25]	244	1			T522	2		T428	2		T832	1
values[26]	307	1			T522	2		T428	10		T832	2
values[27]	238	1			T522	2		T428	9		T832	1
values[28]	245	1			T522	2		T428	12		T832	1
values[29]	246	1			T522	2		T428	3		T832	1
values[30]	277	1			T522	2		T428	4		T832	1
values[31]	237	1			T522	2		T428	12		T832	1
values[32]	250	1			T522	2		T428	10		T832	1
values[33]	265	1			T522	2		T428	12		T832	1
values[34]	239	1			T522	2		T428	7		T832	1
values[35]	275	1			T522	2		T428	3		T832	1
values[36]	245	1			T522	2		T428	6		T832	1
values[37]	239	1			T522	2		T428	6		T832	1
values[38]	207	1			T522	2		T428	4		T832	1
values[39]	249	1			T522	2		T428	10		T832	1
values[40]	257	1			T522	2		T428	17		T832	1
values[41]	228	1			T522	2		T428	7		T832	1
values[42]	265	1			T522	2		T428	4		T832	1
values[43]	231	1			T522	2		T428	6		T832	1
values[44]	238	1			T522	2		T428	7		T832	1
values[45]	313	1			T522	3		T428	8		T832	1
values[46]	247	1			T522	2		T428	3		T832	1
values[47]	216	1			T522	2		T428	7		T832	1
values[48]	236	1			T522	2		T428	15		T832	1
values[49]	238	1			T522	2		T428	5		T832	1
values[50]	215	1			T522	2		T428	8		T832	1
values[51]	220	1			T522	2		T428	3		T832	1
values[52]	228	1			T522	2		T428	4		T832	1
values[53]	224	1			T522	2		T428	9		T832	1
values[54]	236	1			T522	2		T428	5		T832	1
values[55]	206	1			T522	2		T428	8		T832	2
values[56]	213	1			T522	2		T428	6		T832	1
values[57]	177	1			T522	2		T428	9		T832	1
values[58]	181	1			T522	2		T428	8		T832	1
values[59]	188	1			T522	2		T428	3		T832	1
values[60]	187	1			T522	2		T428	3		T832	1
values[61]	200	1			T522	2		T428	6		T832	1
values[62]	189	1			T522	2		T428	7		T832	1
values[63]	181	1			T522	2		T428	3		T832	1
values[64]	188	1			T522	2		T428	4		T832	1
values[65]	209	1			T522	2		T428	14		T832	1
values[66]	160	1			T522	2		T428	17		T832	1
values[67]	170	1			T522	2		T428	6		T832	1
values[68]	161	1			T522	2		T428	4		T832	1
values[69]	192	1			T522	3		T428	8		T832	1
values[70]	133	1			T522	5		T428	5		T832	1
values[71]	93	1			T522	12		T832	1		T855	3
values[72]	90	1			T522	4		T832	1		T855	3
values[73]	74	1			T522	12		T832	1		T855	3
values[74]	78	1			T522	2		T832	1		T855	3
values[75]	75	1			T522	9		T832	1		T855	3
values[76]	62	1			T522	2		T832	1		T855	3
values[77]	49	1			T522	5		T832	1		T855	3
values[78]	61	1			T522	6		T832	1		T855	3
values[79]	58	1			T522	3		T832	1		T855	3
values[80]	62	1			T522	2		T832	2		T855	3
values[81]	75	1			T522	3		T832	1		T855	3
values[82]	63	1			T522	5		T832	1		T855	3
values[83]	66	1			T522	3		T832	1		T855	4
values[84]	75	1			T522	2		T832	1		T855	3
values[85]	71	1			T522	5		T832	1		T855	3
values[86]	78	1			T522	3		T832	1		T855	3
values[87]	66	1			T522	2		T832	1		T855	3
values[88]	63	1			T522	3		T832	1		T855	3
values[89]	76	1			T522	5		T832	1		T855	3
values[90]	64	1			T522	2		T832	1		T855	3
values[91]	62	1			T522	4		T832	1		T855	3
values[92]	72	1			T522	2		T832	1		T855	3
values[93]	62	1			T522	3		T832	1		T855	3
values[94]	94	1			T522	3		T832	1		T855	3
values[95]	79	1			T522	3		T832	1		T855	5
values[96]	56	1			T522	2		T832	1		T855	3
values[97]	59	1			T522	3		T832	1		T855	3
values[98]	95	1			T522	6		T832	1		T855	4
values[99]	92	1			T522	4		T832	1		T855	5
values[100]	88	1			T522	5		T832	1		T855	5
values[101]	83	1			T522	4		T832	1		T855	5
values[102]	65	1			T522	4		T832	1		T855	3
values[103]	73	1			T522	4		T832	1		T855	3
values[104]	70	1			T522	6		T832	1		T855	3
values[105]	95	1			T522	4		T832	1		T855	4
values[106]	82	1			T522	4		T832	1		T855	4
values[107]	85	1			T522	3		T832	1		T855	7
values[108]	76	1			T522	4		T832	1		T855	7
values[109]	71	1			T522	6		T832	1		T855	5
values[110]	85	1			T522	4		T832	1		T855	4
values[111]	83	1			T522	6		T832	1		T855	8
values[112]	100	1			T522	3		T832	1		T855	10
values[113]	66	1			T522	5		T832	1		T855	3
values[114]	68	1			T522	5		T832	1		T855	8
values[115]	91	1			T522	2		T832	1		T855	9
values[116]	85	1			T522	9		T832	1		T855	6
values[117]	65	1			T522	4		T832	1		T855	7
values[118]	72	1			T522	5		T832	1		T855	8
values[119]	70	1			T522	2		T832	1		T855	9
values[120]	70	1			T522	4		T832	1		T855	9
values[121]	71	1			T522	4		T832	1		T855	4
values[122]	54	1			T522	5		T832	3		T855	4
values[123]	71	1			T522	7		T832	4		T855	5
values[124]	72	1			T522	5		T832	1		T855	7
values[125]	80	1			T522	2		T832	3		T855	5
values[126]	173	1			T522	5		T832	2		T855	6
values[127]	916	1			T522	74		T832	34		T855	86
values[128]	7327	1			T522	625		T832	408		T855	897