Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134567	1			T69	99		T70	3		T76	8
values[2]	8253	1			T69	2		T76	1		T463	7
values[3]	2895	1			T522	1		T521	12		T393	2
values[4]	1483	1			T522	1		T521	6		T392	5
values[5]	948	1			T522	1		T521	4		T392	9
values[6]	729	1			T522	1		T521	5		T392	9
values[7]	559	1			T522	1		T521	1		T392	2
values[8]	438	1			T522	1		T392	10		T878	7
values[9]	370	1			T522	1		T392	4		T878	5
values[10]	342	1			T522	1		T392	6		T878	8
values[11]	307	1			T522	1		T392	5		T878	5
values[12]	281	1			T522	1		T392	9		T878	2
values[13]	303	1			T522	1		T392	6		T878	2
values[14]	321	1			T522	1		T392	4		T878	1
values[15]	320	1			T522	1		T392	11		T878	2
values[16]	279	1			T522	1		T392	27		T878	8
values[17]	246	1			T522	1		T392	4		T878	2
values[18]	340	1			T522	1		T392	4		T878	3
values[19]	287	1			T522	1		T392	6		T878	3
values[20]	298	1			T522	1		T392	9		T878	2
values[21]	305	1			T522	1		T392	9		T878	2
values[22]	292	1			T522	1		T392	2		T878	4
values[23]	296	1			T522	1		T392	9		T878	2
values[24]	277	1			T522	1		T392	9		T878	4
values[25]	272	1			T522	1		T392	10		T878	4
values[26]	262	1			T522	1		T392	13		T832	1
values[27]	282	1			T522	1		T392	6		T832	1
values[28]	316	1			T522	1		T392	3		T832	1
values[29]	305	1			T522	1		T392	17		T832	1
values[30]	287	1			T522	1		T392	12		T832	1
values[31]	276	1			T522	1		T392	6		T832	1
values[32]	277	1			T522	1		T392	4		T832	1
values[33]	258	1			T522	1		T392	4		T832	1
values[34]	313	1			T522	1		T392	4		T832	1
values[35]	225	1			T522	1		T392	2		T832	1
values[36]	261	1			T522	1		T392	7		T832	1
values[37]	273	1			T522	1		T392	12		T832	1
values[38]	317	1			T522	1		T392	13		T832	1
values[39]	235	1			T522	1		T392	3		T832	1
values[40]	222	1			T522	1		T392	10		T832	1
values[41]	273	1			T522	1		T392	10		T832	1
values[42]	249	1			T522	1		T392	4		T832	1
values[43]	293	1			T522	1		T392	3		T832	1
values[44]	229	1			T522	1		T392	4		T832	1
values[45]	258	1			T522	1		T392	6		T832	1
values[46]	226	1			T522	1		T392	11		T832	1
values[47]	258	1			T522	1		T392	10		T832	1
values[48]	250	1			T522	1		T392	3		T832	1
values[49]	244	1			T522	1		T392	10		T832	1
values[50]	243	1			T522	1		T392	5		T832	1
values[51]	216	1			T522	1		T392	22		T832	1
values[52]	232	1			T522	1		T392	19		T832	1
values[53]	208	1			T522	1		T392	7		T832	1
values[54]	238	1			T522	1		T392	9		T832	1
values[55]	205	1			T522	1		T832	1		T846	2
values[56]	198	1			T522	1		T832	1		T846	2
values[57]	197	1			T522	1		T832	1		T846	2
values[58]	210	1			T522	1		T832	1		T846	2
values[59]	190	1			T522	1		T832	1		T846	2
values[60]	171	1			T522	1		T832	1		T846	2
values[61]	153	1			T522	1		T832	1		T846	2
values[62]	138	1			T522	1		T832	1		T846	2
values[63]	170	1			T522	1		T832	1		T846	2
values[64]	213	1			T522	1		T832	1		T846	2
values[65]	216	1			T522	1		T832	1		T846	2
values[66]	211	1			T522	1		T832	1		T846	2
values[67]	201	1			T522	1		T832	1		T846	2
values[68]	145	1			T522	1		T832	1		T846	2
values[69]	136	1			T522	1		T832	1		T846	2
values[70]	134	1			T522	1		T832	1		T846	2
values[71]	150	1			T522	1		T832	1		T846	2
values[72]	129	1			T522	1		T832	1		T846	2
values[73]	130	1			T522	1		T832	1		T846	2
values[74]	145	1			T522	1		T832	1		T846	2
values[75]	108	1			T522	1		T832	1		T846	2
values[76]	97	1			T522	1		T832	1		T846	2
values[77]	84	1			T522	1		T832	1		T846	2
values[78]	105	1			T522	1		T832	1		T846	2
values[79]	81	1			T522	1		T832	1		T846	2
values[80]	105	1			T522	1		T832	1		T846	2
values[81]	86	1			T522	1		T832	1		T846	2
values[82]	80	1			T522	1		T832	1		T846	2
values[83]	86	1			T522	1		T832	1		T846	2
values[84]	109	1			T522	1		T832	1		T846	2
values[85]	108	1			T522	1		T832	1		T846	5
values[86]	103	1			T522	1		T832	1		T846	2
values[87]	108	1			T522	1		T832	3		T846	4
values[88]	77	1			T522	1		T832	3		T846	2
values[89]	90	1			T522	1		T832	1		T846	8
values[90]	91	1			T522	1		T832	6		T846	11
values[91]	105	1			T522	1		T832	6		T846	5
values[92]	107	1			T522	1		T832	3		T846	5
values[93]	92	1			T522	1		T832	2		T846	5
values[94]	85	1			T522	1		T832	2		T846	4
values[95]	75	1			T522	1		T832	1		T846	3
values[96]	90	1			T522	1		T832	3		T846	3
values[97]	104	1			T522	1		T832	1		T846	4
values[98]	98	1			T522	1		T832	5		T846	2
values[99]	99	1			T522	1		T832	4		T846	2
values[100]	114	1			T522	1		T832	2		T846	2
values[101]	104	1			T522	2		T832	3		T846	2
values[102]	115	1			T522	1		T832	5		T846	4
values[103]	105	1			T522	1		T832	10		T846	7
values[104]	100	1			T522	1		T832	1		T846	4
values[105]	121	1			T522	1		T832	3		T846	8
values[106]	90	1			T522	1		T832	3		T846	3
values[107]	88	1			T522	1		T832	1		T846	5
values[108]	87	1			T522	1		T832	2		T846	9
values[109]	76	1			T522	1		T832	2		T846	3
values[110]	73	1			T522	1		T832	1		T846	4
values[111]	78	1			T522	1		T832	1		T846	4
values[112]	81	1			T522	3		T832	2		T846	3
values[113]	69	1			T522	2		T832	1		T846	5
values[114]	81	1			T522	2		T832	3		T846	5
values[115]	86	1			T522	1		T832	6		T846	3
values[116]	91	1			T522	5		T832	5		T846	3
values[117]	68	1			T522	4		T832	6		T846	2
values[118]	76	1			T522	2		T832	2		T846	7
values[119]	78	1			T522	1		T832	2		T846	4
values[120]	85	1			T522	2		T832	1		T846	6
values[121]	107	1			T522	1		T832	3		T846	8
values[122]	92	1			T522	4		T832	1		T846	6
values[123]	73	1			T522	1		T832	1		T846	5
values[124]	66	1			T522	1		T832	3		T846	2
values[125]	78	1			T522	2		T832	1		T846	8
values[126]	144	1			T522	3		T832	4		T846	2
values[127]	1069	1			T522	32		T832	30		T846	66
values[128]	9542	1			T522	316		T832	272		T846	602