Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	468	1			T701	2		T521	1		T829	1
all_values[1]	436	1			T829	1		T443	1		T587	1
all_values[2]	455	1			T521	2		T443	7		T840	1
all_values[3]	477	1			T701	1		T443	1		T668	1
all_values[4]	454	1			T701	1		T521	2		T443	2
all_values[5]	471	1			T701	1		T522	1		T521	1
all_values[6]	477	1			T443	1		T587	1		T566	2
all_values[7]	438	1			T329	1		T829	1		T443	2
all_values[8]	438	1			T701	1		T443	2		T587	3
all_values[9]	401	1			T329	1		T521	1		T829	1
all_values[10]	448	1			T522	1		T443	2		T664	1
all_values[11]	461	1			T521	3		T829	1		T443	3
all_values[12]	451	1			T329	1		T668	1		T587	2
all_values[13]	417	1			T329	1		T701	1		T521	1
all_values[14]	487	1			T521	1		T829	1		T443	3
all_values[15]	453	1			T521	2		T829	1		T443	1
all_values[16]	452	1			T443	4		T587	2		T640	1
all_values[17]	448	1			T443	3		T372	1		T668	1
all_values[18]	484	1			T701	1		T829	1		T443	1
all_values[19]	407	1			T521	1		T443	3		T840	1
all_values[20]	429	1			T701	1		T668	1		T587	2
all_values[21]	445	1			T443	2		T668	3		T587	1
all_values[22]	469	1			T522	1		T443	6		T664	1
all_values[23]	439	1			T522	1		T521	1		T443	3
all_values[24]	465	1			T521	1		T443	4		T664	1
all_values[25]	477	1			T522	2		T521	1		T829	2
all_values[26]	450	1			T522	1		T521	1		T443	3
all_values[27]	445	1			T329	1		T521	1		T443	4
all_values[28]	451	1			T701	1		T443	3		T664	1
all_values[29]	439	1			T522	1		T443	1		T668	1
all_values[30]	467	1			T701	1		T829	1		T587	3
all_values[31]	499	1			T701	3		T521	1		T443	1
all_values[32]	430	1			T443	1		T668	1		T587	2
all_values[33]	478	1			T443	2		T840	1		T664	1
all_values[34]	496	1			T329	1		T443	4		T664	1
all_values[35]	501	1			T829	1		T443	5		T664	1
all_values[36]	423	1			T443	4		T668	2		T587	3
all_values[37]	461	1			T329	2		T701	1		T443	3
all_values[38]	463	1			T443	1		T664	1		T668	1
all_values[39]	467	1			T329	1		T522	1		T521	3
all_values[40]	469	1			T329	1		T521	1		T443	1
all_values[41]	434	1			T701	1		T443	4		T664	2
all_values[42]	455	1			T829	1		T443	2		T840	1
all_values[43]	462	1			T829	1		T840	1		T587	1
all_values[44]	503	1			T829	1		T443	2		T587	3
all_values[45]	447	1			T443	1		T668	2		T587	2
all_values[46]	462	1			T829	1		T443	3		T668	2
all_values[47]	454	1			T329	1		T829	2		T443	2
all_values[48]	437	1			T521	1		T829	1		T443	2
all_values[49]	473	1			T522	1		T668	4		T587	3