Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3277	1			T78	5		T521	5		T370	5
all_values[1]	3292	1			T78	2		T521	5		T370	1
all_values[2]	3224	1			T78	1		T521	2		T423	2
all_values[3]	3285	1			T78	2		T521	1		T370	3
all_values[4]	3353	1			T78	3		T521	7		T370	5
all_values[5]	3356	1			T78	3		T370	3		T423	2
all_values[6]	3350	1			T78	1		T521	5		T370	1
all_values[7]	3310	1			T78	1		T521	2		T423	2
all_values[8]	3310	1			T78	2		T370	1		T423	2
all_values[9]	3296	1			T78	4		T521	1		T370	2
all_values[10]	3358	1			T78	2		T521	4		T370	2
all_values[11]	3221	1			T78	4		T521	1		T370	2
all_values[12]	3353	1			T78	1		T521	1		T370	8
all_values[13]	3295	1			T78	2		T521	2		T370	4
all_values[14]	3268	1			T78	1		T521	2		T370	4
all_values[15]	3283	1			T78	2		T521	2		T370	2
all_values[16]	3472	1			T521	5		T370	1		T423	5
all_values[17]	3350	1			T78	2		T521	3		T370	5
all_values[18]	3342	1			T78	6		T370	2		T423	1
all_values[19]	3421	1			T78	3		T521	1		T370	1
all_values[20]	3296	1			T78	2		T521	5		T370	6
all_values[21]	3356	1			T78	4		T521	3		T370	2
all_values[22]	3253	1			T78	2		T370	3		T423	2
all_values[23]	3282	1			T78	1		T370	6		T423	6
all_values[24]	3346	1			T521	3		T370	3		T423	6
all_values[25]	3241	1			T521	4		T370	2		T423	2
all_values[26]	3230	1			T78	2		T521	8		T370	5
all_values[27]	3302	1			T78	1		T521	3		T370	3
all_values[28]	3376	1			T521	4		T370	3		T423	2
all_values[29]	3270	1			T78	1		T423	1		T443	30
all_values[30]	3272	1			T78	2		T521	2		T370	4
all_values[31]	3270	1			T78	3		T370	5		T423	4
all_values[32]	3294	1			T78	3		T521	2		T370	1
all_values[33]	3300	1			T78	2		T521	3		T370	1
all_values[34]	3353	1			T78	2		T521	7		T370	2
all_values[35]	3264	1			T521	2		T370	6		T423	4
all_values[36]	3286	1			T78	1		T521	5		T370	3
all_values[37]	3294	1			T78	2		T423	4		T443	32
all_values[38]	3303	1			T78	1		T521	5		T370	2
all_values[39]	3292	1			T78	2		T521	3		T370	3
all_values[40]	3219	1			T78	1		T521	4		T370	4
all_values[41]	3271	1			T78	1		T521	8		T370	3
all_values[42]	3278	1			T78	1		T521	5		T370	3
all_values[43]	3334	1			T78	3		T370	3		T423	3
all_values[44]	3333	1			T78	1		T521	4		T370	2
all_values[45]	3268	1			T78	2		T521	3		T370	2
all_values[46]	3278	1			T78	1		T521	3		T370	3
all_values[47]	3311	1			T521	4		T370	4		T423	2
all_values[48]	3431	1			T78	3		T521	2		T370	5
all_values[49]	3295	1			T78	2		T521	4		T370	3
all_values[50]	3227	1			T78	1		T521	3		T370	4
all_values[51]	3297	1			T78	1		T521	3		T370	4
all_values[52]	3290	1			T521	4		T370	2		T423	2
all_values[53]	3385	1			T78	3		T521	4		T370	3
all_values[54]	3265	1			T78	1		T521	5		T370	1
all_values[55]	3355	1			T78	2		T521	1		T370	5
all_values[56]	3164	1			T78	1		T521	1		T370	7
all_values[57]	3322	1			T78	2		T521	2		T370	5
all_values[58]	3358	1			T78	3		T370	4		T423	1
all_values[59]	3344	1			T78	2		T521	1		T370	2
all_values[60]	3352	1			T78	1		T521	2		T370	6
all_values[61]	3244	1			T78	1		T521	4		T370	5
all_values[62]	3283	1			T78	3		T521	4		T370	2
all_values[63]	3206	1			T78	3		T370	1		T423	4