CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 376646 | 1 | T67 | 56 | T210 | 289 | T405 | 3 | ||||
rising | 376728 | 1 | T67 | 56 | T210 | 289 | T405 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1063624 | 1 | T67 | 172 | T210 | 1146 | T405 | 6 | ||||
auto[1] | 9322674 | 1 | T66 | 3370 | T67 | 505 | T72 | 2070 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 333379 | 1 | T67 | 84 | T210 | 355 | T405 | 1 | ||||
rising | 333467 | 1 | T67 | 84 | T73 | 1 | T210 | 356 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1185410 | 1 | T67 | 212 | T73 | 2 | T210 | 1452 | ||||
auto[1] | 10047488 | 1 | T66 | 3800 | T67 | 1392 | T72 | 2230 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 662113 | 1 | T67 | 110 | T73 | 2 | T210 | 503 | ||||
rising | 662175 | 1 | T67 | 110 | T73 | 2 | T210 | 503 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1072261 | 1 | T67 | 187 | T73 | 2 | T210 | 1184 | ||||
auto[1] | 9420078 | 1 | T66 | 3434 | T67 | 507 | T72 | 2562 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7049 | 1 | T459 | 1 | T507 | 1 | T495 | 106 | ||||
rising | 7087 | 1 | T459 | 1 | T507 | 1 | T495 | 106 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 174099 | 1 | T67 | 11 | T72 | 54 | T73 | 112 | ||||
auto[1] | 13839 | 1 | T459 | 1 | T507 | 1 | T495 | 194 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4969 | 1 | T502 | 1 | T496 | 1 | T495 | 4 | ||||
rising | 5000 | 1 | T502 | 1 | T496 | 1 | T495 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 187643 | 1 | T67 | 2 | T72 | 48 | T73 | 105 | ||||
auto[1] | 7546 | 1 | T502 | 1 | T496 | 1 | T495 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2996 | 1 | T72 | 1 | T496 | 1 | T498 | 2 | ||||
rising | 3023 | 1 | T72 | 1 | T496 | 1 | T498 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 172484 | 1 | T67 | 4 | T72 | 42 | T73 | 117 | ||||
auto[1] | 3266 | 1 | T72 | 1 | T496 | 1 | T498 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6028 | 1 | T210 | 2 | T502 | 1 | T496 | 1 | ||||
rising | 6076 | 1 | T210 | 2 | T502 | 1 | T496 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 168304 | 1 | T67 | 4 | T72 | 43 | T73 | 135 | ||||
auto[1] | 15492 | 1 | T210 | 2 | T502 | 1 | T496 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3858 | 1 | T210 | 1 | T498 | 1 | T495 | 9 | ||||
rising | 3877 | 1 | T210 | 1 | T498 | 1 | T495 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 182734 | 1 | T67 | 4 | T72 | 44 | T73 | 113 | ||||
auto[1] | 4333 | 1 | T210 | 1 | T498 | 1 | T495 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5282 | 1 | T408 | 4 | T500 | 1 | T389 | 3 | ||||
rising | 5313 | 1 | T408 | 4 | T500 | 1 | T389 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 168176 | 1 | T67 | 3 | T72 | 47 | T73 | 110 | ||||
auto[1] | 10154 | 1 | T408 | 4 | T500 | 1 | T389 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6131 | 1 | T66 | 59 | T496 | 1 | T501 | 1 | ||||
rising | 6181 | 1 | T66 | 59 | T502 | 1 | T496 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 190244 | 1 | T66 | 426 | T67 | 9 | T72 | 46 | ||||
auto[1] | 12089 | 1 | T66 | 73 | T502 | 1 | T496 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7456 | 1 | T210 | 1 | T388 | 104 | T470 | 2 | ||||
rising | 7497 | 1 | T210 | 1 | T388 | 105 | T470 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 180484 | 1 | T67 | 3 | T72 | 51 | T73 | 94 | ||||
auto[1] | 18319 | 1 | T210 | 1 | T388 | 346 | T470 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5208 | 1 | T210 | 2 | T496 | 1 | T501 | 1 | ||||
rising | 5257 | 1 | T210 | 2 | T496 | 1 | T501 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 176583 | 1 | T67 | 9 | T72 | 39 | T73 | 106 | ||||
auto[1] | 9892 | 1 | T210 | 2 | T496 | 1 | T501 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6745 | 1 | T66 | 39 | T210 | 1 | T388 | 104 | ||||
rising | 6780 | 1 | T66 | 39 | T210 | 1 | T388 | 104 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 186965 | 1 | T66 | 437 | T67 | 4 | T72 | 42 | ||||
auto[1] | 10665 | 1 | T66 | 43 | T210 | 1 | T388 | 208 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5693 | 1 | T388 | 101 | T496 | 1 | T495 | 26 | ||||
rising | 5725 | 1 | T388 | 101 | T496 | 1 | T495 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 180000 | 1 | T67 | 120 | T72 | 40 | T73 | 103 | ||||
auto[1] | 7414 | 1 | T388 | 132 | T496 | 1 | T495 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 15104 | 1 | T66 | 6 | T67 | 1 | T74 | 1 | ||||
rising | 15131 | 1 | T66 | 6 | T67 | 1 | T74 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1441148 | 1 | T66 | 459 | T67 | 168 | T72 | 347 | ||||
auto[1] | 15781 | 1 | T66 | 6 | T67 | 1 | T74 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4757 | 1 | T66 | 105 | T210 | 1 | T404 | 7 | ||||
rising | 4793 | 1 | T66 | 106 | T210 | 1 | T404 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 174996 | 1 | T66 | 228 | T67 | 5 | T72 | 52 | ||||
auto[1] | 9619 | 1 | T66 | 244 | T210 | 1 | T404 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8297 | 1 | T74 | 1 | T406 | 15 | T404 | 1 | ||||
rising | 8348 | 1 | T74 | 1 | T406 | 15 | T404 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 173526 | 1 | T67 | 7 | T72 | 45 | T73 | 104 | ||||
auto[1] | 23668 | 1 | T74 | 1 | T406 | 15 | T404 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 1933 | 1 | T496 | 1 | T404 | 1 | T459 | 1 | ||||
rising | 1952 | 1 | T496 | 1 | T404 | 1 | T459 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 177480 | 1 | T67 | 3 | T72 | 40 | T73 | 104 | ||||
auto[1] | 2039 | 1 | T496 | 1 | T404 | 1 | T459 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6328 | 1 | T73 | 2 | T496 | 1 | T498 | 1 | ||||
rising | 6364 | 1 | T73 | 2 | T496 | 1 | T498 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 170896 | 1 | T67 | 2 | T72 | 44 | T73 | 117 | ||||
auto[1] | 12434 | 1 | T73 | 2 | T496 | 1 | T498 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8140 | 1 | T66 | 20 | T505 | 1 | T495 | 2 | ||||
rising | 8179 | 1 | T66 | 20 | T505 | 1 | T495 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 178549 | 1 | T66 | 451 | T67 | 4 | T72 | 48 | ||||
auto[1] | 17117 | 1 | T66 | 23 | T505 | 1 | T495 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5435 | 1 | T406 | 1 | T498 | 17 | T470 | 1 | ||||
rising | 5482 | 1 | T406 | 1 | T498 | 17 | T470 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 162337 | 1 | T67 | 10 | T72 | 34 | T73 | 102 | ||||
auto[1] | 10543 | 1 | T406 | 1 | T498 | 19 | T470 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5827 | 1 | T210 | 1 | T496 | 2 | T404 | 1 | ||||
rising | 5865 | 1 | T210 | 1 | T496 | 2 | T404 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 188690 | 1 | T67 | 8 | T72 | 50 | T73 | 108 | ||||
auto[1] | 9003 | 1 | T210 | 1 | T496 | 2 | T404 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2676 | 1 | T470 | 1 | T495 | 21 | T389 | 4 | ||||
rising | 2695 | 1 | T470 | 1 | T495 | 21 | T389 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 188759 | 1 | T67 | 9 | T72 | 51 | T73 | 130 | ||||
auto[1] | 2864 | 1 | T470 | 1 | T495 | 21 | T389 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6787 | 1 | T210 | 1 | T502 | 1 | T496 | 1 | ||||
rising | 6826 | 1 | T210 | 1 | T502 | 1 | T496 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 165961 | 1 | T67 | 7 | T72 | 57 | T73 | 125 | ||||
auto[1] | 10781 | 1 | T210 | 1 | T502 | 1 | T496 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 42698 | 1 | T499 | 1671 | T509 | 1828 | T510 | 1409 | ||||
rising | 42704 | 1 | T499 | 1672 | T509 | 1828 | T510 | 1409 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 92066 | 1 | T499 | 3730 | T509 | 4035 | T510 | 2865 | ||||
auto[1] | 82909 | 1 | T499 | 3194 | T509 | 3603 | T510 | 2730 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 24455 | 1 | T499 | 986 | T509 | 1075 | T510 | 768 | ||||
rising | 24447 | 1 | T499 | 986 | T509 | 1075 | T510 | 768 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 144549 | 1 | T499 | 5695 | T509 | 6328 | T510 | 4662 | ||||
auto[1] | 30426 | 1 | T499 | 1229 | T509 | 1310 | T510 | 933 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 24455 | 1 | T499 | 986 | T509 | 1075 | T510 | 768 | ||||
rising | 24447 | 1 | T499 | 986 | T509 | 1075 | T510 | 768 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 144549 | 1 | T499 | 5695 | T509 | 6328 | T510 | 4662 | ||||
auto[1] | 30426 | 1 | T499 | 1229 | T509 | 1310 | T510 | 933 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4116 | 1 | T499 | 233 | T509 | 225 | T510 | 92 | ||||
rising | 4105 | 1 | T499 | 233 | T509 | 224 | T510 | 91 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 168972 | 1 | T499 | 6597 | T509 | 7314 | T510 | 5472 | ||||
auto[1] | 6003 | 1 | T499 | 327 | T509 | 324 | T510 | 123 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 97155 | 1 | T68 | 609 | T336 | 554 | T499 | 4 | ||||
rising | 97173 | 1 | T68 | 609 | T336 | 554 | T499 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 24175724 | 1 | T1 | 18586 | T2 | 54667 | T3 | 4524 | ||||
auto[1] | 586193 | 1 | T68 | 772 | T336 | 700 | T499 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 43024 | 1 | T499 | 1691 | T509 | 1864 | T510 | 1396 | ||||
rising | 43031 | 1 | T499 | 1692 | T509 | 1864 | T510 | 1397 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 92285 | 1 | T499 | 3724 | T509 | 3986 | T510 | 2981 | ||||
auto[1] | 82690 | 1 | T499 | 3200 | T509 | 3652 | T510 | 2614 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 36975 | 1 | T499 | 1479 | T509 | 1619 | T510 | 1181 | ||||
rising | 36976 | 1 | T499 | 1479 | T509 | 1620 | T510 | 1181 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 121920 | 1 | T499 | 4853 | T509 | 5392 | T510 | 3825 | ||||
auto[1] | 53055 | 1 | T499 | 2071 | T509 | 2246 | T510 | 1770 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2345 | 1 | T459 | 2 | T507 | 2 | T495 | 2 | ||||
rising | 2365 | 1 | T459 | 2 | T507 | 2 | T495 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 192777 | 1 | T67 | 5 | T72 | 52 | T73 | 123 | ||||
auto[1] | 2473 | 1 | T459 | 2 | T507 | 3 | T495 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2832 | 1 | T459 | 2 | T470 | 1 | T507 | 1 | ||||
rising | 2852 | 1 | T459 | 2 | T470 | 1 | T507 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 185900 | 1 | T67 | 24 | T72 | 45 | T73 | 102 | ||||
auto[1] | 3023 | 1 | T459 | 2 | T470 | 1 | T507 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6627 | 1 | T72 | 1 | T406 | 69 | T388 | 38 | ||||
rising | 6682 | 1 | T72 | 1 | T406 | 69 | T388 | 39 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 160328 | 1 | T67 | 5 | T72 | 45 | T73 | 109 | ||||
auto[1] | 26481 | 1 | T72 | 1 | T406 | 76 | T388 | 478 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6900 | 1 | T495 | 185 | T408 | 2 | T389 | 5 | ||||
rising | 6955 | 1 | T495 | 185 | T408 | 2 | T389 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 162837 | 1 | T67 | 8 | T72 | 46 | T73 | 94 | ||||
auto[1] | 18787 | 1 | T495 | 584 | T408 | 2 | T389 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2925 | 1 | T210 | 1 | T388 | 39 | T502 | 1 | ||||
rising | 2956 | 1 | T210 | 1 | T388 | 39 | T502 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 176520 | 1 | T67 | 6 | T72 | 39 | T73 | 108 | ||||
auto[1] | 3091 | 1 | T210 | 1 | T388 | 42 | T502 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7678 | 1 | T210 | 1 | T406 | 104 | T496 | 1 | ||||
rising | 7722 | 1 | T210 | 1 | T406 | 105 | T496 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 172155 | 1 | T67 | 8 | T72 | 46 | T73 | 110 | ||||
auto[1] | 15328 | 1 | T210 | 1 | T406 | 163 | T496 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6581 | 1 | T73 | 1 | T496 | 3 | T498 | 1 | ||||
rising | 6628 | 1 | T73 | 1 | T496 | 3 | T498 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 166035 | 1 | T67 | 5 | T72 | 47 | T73 | 114 | ||||
auto[1] | 13002 | 1 | T73 | 1 | T496 | 3 | T498 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6078 | 1 | T210 | 1 | T388 | 93 | T496 | 3 | ||||
rising | 6116 | 1 | T210 | 1 | T388 | 94 | T496 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 182419 | 1 | T67 | 7 | T72 | 41 | T73 | 124 | ||||
auto[1] | 12657 | 1 | T210 | 1 | T388 | 336 | T496 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 21890 | 1 | T66 | 8 | T72 | 5 | T73 | 8 | ||||
rising | 21923 | 1 | T66 | 8 | T72 | 5 | T73 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1425901 | 1 | T66 | 476 | T67 | 165 | T72 | 307 | ||||
auto[1] | 22934 | 1 | T66 | 8 | T72 | 5 | T73 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 9054 | 1 | T496 | 1 | T498 | 5 | T470 | 1 | ||||
rising | 9112 | 1 | T496 | 1 | T498 | 5 | T470 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 174151 | 1 | T67 | 11 | T72 | 43 | T73 | 97 | ||||
auto[1] | 19318 | 1 | T496 | 1 | T498 | 5 | T470 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5353 | 1 | T66 | 70 | T210 | 1 | T502 | 1 | ||||
rising | 5386 | 1 | T66 | 70 | T210 | 1 | T502 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 177105 | 1 | T66 | 420 | T67 | 3 | T72 | 38 | ||||
auto[1] | 8360 | 1 | T66 | 87 | T210 | 1 | T502 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 193545 | 1 | T73 | 293 | T210 | 114 | T404 | 96 | ||||
rising | 193548 | 1 | T73 | 293 | T210 | 114 | T404 | 96 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1740547 | 1 | T73 | 2586 | T210 | 1011 | T404 | 843 | ||||
auto[1] | 217982 | 1 | T73 | 337 | T210 | 129 | T404 | 104 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 480686 | 1 | T73 | 717 | T210 | 273 | T404 | 231 | ||||
rising | 480703 | 1 | T73 | 716 | T210 | 274 | T404 | 230 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 869492 | 1 | T73 | 1295 | T210 | 517 | T404 | 430 | ||||
auto[1] | 1089037 | 1 | T73 | 1628 | T210 | 623 | T404 | 517 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 480686 | 1 | T73 | 717 | T210 | 273 | T404 | 231 | ||||
rising | 480703 | 1 | T73 | 716 | T210 | 274 | T404 | 230 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 869492 | 1 | T73 | 1295 | T210 | 517 | T404 | 430 | ||||
auto[1] | 1089037 | 1 | T73 | 1628 | T210 | 623 | T404 | 517 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |