Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.89	95.29	93.76	94.97		94.48	97.20	99.64

Total tests in report: 2823

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.50	40.50	45.93	45.93	43.22	43.22	32.19	32.19			58.31	58.31	63.03	63.03	0.34	0.34	/workspace/coverage/default/56.chip_sw_all_escalation_resets.1056696334
52.55	12.05	57.90	11.97	60.33	17.11	38.54	6.35			69.71	11.40	87.43	24.40	1.40	1.06	/workspace/coverage/cover_reg_top/4.chip_csr_rw.2814482812
57.69	5.13	68.91	11.01	67.80	7.47	41.04	2.50			79.54	9.83	87.43	0.00	1.40	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.108057580
62.11	4.42	73.45	4.54	68.83	1.04	41.94	0.90			79.67	0.13	87.43	0.00	21.33	19.93	/workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.900667463
65.35	3.24	73.45	0.00	68.83	0.00	41.94	0.00			79.67	0.00	87.43	0.00	40.77	19.45	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.4176033471
68.16	2.81	75.42	1.97	71.37	2.54	51.81	9.86			81.59	1.91	87.99	0.55	40.77	0.00	/workspace/coverage/default/1.rom_raw_unlock.3256454479
70.53	2.37	80.82	5.41	75.23	3.86	55.27	3.46			83.09	1.51	87.99	0.00	40.77	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.387041918
72.86	2.33	80.82	0.00	75.23	0.00	69.27	14.00			83.09	0.00	87.99	0.00	40.77	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1603184454
75.06	2.20	80.82	0.00	75.48	0.25	69.27	0.00			83.16	0.07	87.99	0.00	53.67	12.90	/workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1996521131
76.76	1.70	80.82	0.00	75.48	0.00	69.27	0.00			83.16	0.00	87.99	0.00	63.86	10.19	/workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3899418052
78.33	1.56	82.25	1.42	76.11	0.63	71.22	1.95			83.20	0.04	87.99	0.00	69.19	5.33	/workspace/coverage/cover_reg_top/39.xbar_error_random.3634913068
79.84	1.52	83.94	1.69	77.42	1.32	71.83	0.61			84.57	1.37	92.05	4.07	69.24	0.05	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3913678952
81.27	1.43	83.94	0.00	77.78	0.36	71.83	0.00			84.67	0.10	92.05	0.00	77.37	8.13	/workspace/coverage/cover_reg_top/22.xbar_stress_all.218143177
82.58	1.31	85.95	2.01	80.70	2.92	72.11	0.28			87.30	2.64	92.05	0.00	77.37	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3514554115
83.66	1.08	86.55	0.60	81.08	0.38	76.99	4.88			87.90	0.60	92.05	0.00	77.37	0.00	/workspace/coverage/default/1.chip_sw_otbn_randomness.904559166
84.55	0.89	87.32	0.77	81.33	0.25	77.01	0.02			88.18	0.27	96.12	4.07	77.37	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2281916000
85.43	0.88	87.66	0.34	81.64	0.31	80.94	3.93			88.42	0.24	96.12	0.00	77.83	0.46	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1663177834
86.23	0.80	87.67	0.01	82.21	0.57	80.94	0.00			88.42	0.01	96.12	0.00	82.02	4.19	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2408498351
86.93	0.70	87.67	0.00	82.21	0.00	80.94	0.00			88.42	0.00	96.12	0.00	86.22	4.19	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1716309750
87.58	0.65	88.90	1.23	83.20	0.99	81.45	0.51			89.59	1.16	96.12	0.00	86.22	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1464609574
88.19	0.61	88.92	0.02	83.24	0.04	83.34	1.89			89.59	0.00	96.12	0.00	87.92	1.70	/workspace/coverage/default/1.chip_sw_alert_test.380645063
88.77	0.58	88.92	0.00	83.24	0.00	86.84	3.51			89.59	0.00	96.12	0.00	87.92	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1865044205
89.32	0.55	90.14	1.22	84.11	0.87	87.38	0.53			90.25	0.67	96.12	0.00	87.92	0.00	/workspace/coverage/default/0.chip_sw_gpio.2139636767
89.85	0.53	90.14	0.00	84.11	0.00	87.38	0.00			90.25	0.00	96.12	0.00	91.08	3.16	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1840992468
90.36	0.51	90.15	0.01	86.76	2.65	87.38	0.00			90.25	0.00	96.12	0.00	91.51	0.42	/workspace/coverage/cover_reg_top/16.chip_tl_errors.2040726707
90.77	0.41	91.03	0.88	87.65	0.89	87.40	0.02			90.91	0.66	96.12	0.00	91.52	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1061922598
91.14	0.37	91.03	0.00	87.65	0.00	87.40	0.00			90.91	0.00	96.12	0.00	93.75	2.23	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3075595036
91.51	0.37	91.59	0.56	88.14	0.49	88.08	0.68			91.41	0.49	96.12	0.00	93.75	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.705401405
91.86	0.35	92.25	0.66	88.65	0.50	88.21	0.13			92.21	0.80	96.12	0.00	93.75	0.00	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2210596516
92.19	0.33	92.85	0.60	89.58	0.93	88.25	0.04			92.61	0.40	96.12	0.00	93.75	0.00	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1300052755
92.47	0.28	93.57	0.72	89.70	0.12	88.33	0.08			92.62	0.01	96.12	0.00	94.49	0.74	/workspace/coverage/cover_reg_top/99.xbar_access_same_device.1179386930
92.74	0.26	93.57	0.00	89.70	0.00	88.33	0.00			92.62	0.00	96.12	0.00	96.08	1.59	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.817697113
92.91	0.17	93.59	0.02	90.18	0.48	88.36	0.03			93.14	0.52	96.12	0.00	96.08	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.865789981
93.08	0.16	93.72	0.13	90.25	0.07	89.07	0.71			93.21	0.07	96.12	0.00	96.08	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4055266013
93.23	0.16	94.00	0.28	90.50	0.26	89.16	0.09			93.53	0.32	96.12	0.00	96.08	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3848658780
93.38	0.14	94.00	0.00	90.56	0.06	89.16	0.00			93.53	0.00	96.12	0.00	96.89	0.81	/workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3624055177
93.52	0.14	94.00	0.00	90.56	0.00	89.99	0.83			93.53	0.00	96.12	0.00	96.89	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2743985363
93.64	0.12	94.18	0.17	90.83	0.27	90.27	0.28			93.53	0.00	96.12	0.00	96.89	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1323150576
93.75	0.12	94.18	0.00	90.83	0.00	90.94	0.66			93.53	0.00	96.12	0.00	96.92	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1442203579
93.86	0.10	94.18	0.00	90.84	0.01	90.94	0.00			93.53	0.00	96.12	0.00	97.54	0.62	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.737925073
93.95	0.10	94.19	0.01	90.90	0.06	91.23	0.29			93.56	0.02	96.30	0.18	97.54	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4206397167
94.05	0.10	94.26	0.07	91.08	0.17	91.47	0.24			93.64	0.08	96.30	0.00	97.54	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4259305970
94.14	0.09	94.26	0.00	91.32	0.25	91.47	0.00			93.91	0.27	96.30	0.00	97.54	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2373240031
94.22	0.09	94.34	0.08	91.32	0.00	91.90	0.43			93.92	0.01	96.30	0.00	97.54	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.1304389620
94.30	0.08	94.34	0.00	91.33	0.01	92.39	0.49			93.92	0.00	96.30	0.00	97.54	0.00	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3825642384
94.39	0.08	94.34	0.00	91.38	0.05	92.39	0.00			93.94	0.02	96.30	0.00	97.97	0.42	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.4161607707
94.46	0.08	94.35	0.01	91.38	0.01	92.83	0.44			93.94	0.00	96.30	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2004711963
94.53	0.07	94.35	0.00	91.79	0.41	92.83	0.00			93.94	0.00	96.30	0.00	97.97	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.915396889
94.59	0.06	94.35	0.00	91.81	0.02	93.02	0.18			93.94	0.00	96.30	0.00	98.12	0.15	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1842877450
94.64	0.06	94.42	0.08	91.91	0.10	93.10	0.08			94.02	0.08	96.30	0.00	98.12	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2173471595
94.70	0.05	94.43	0.01	91.91	0.01	93.40	0.30			94.02	0.00	96.30	0.00	98.12	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2905396902
94.75	0.05	94.43	0.00	91.91	0.00	93.69	0.29			94.02	0.00	96.30	0.00	98.12	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.808317907
94.79	0.05	94.43	0.00	91.91	0.00	93.97	0.27			94.02	0.00	96.30	0.00	98.12	0.00	/workspace/coverage/default/2.chip_sw_kmac_entropy.345091230
94.84	0.04	94.47	0.03	91.91	0.01	94.00	0.03			94.03	0.02	96.49	0.18	98.12	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2635242837
94.88	0.04	94.49	0.02	91.94	0.03	94.00	0.00			94.05	0.02	96.67	0.18	98.13	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3701938904
94.92	0.04	94.50	0.01	91.96	0.01	94.00	0.00			94.08	0.02	96.86	0.18	98.14	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2642541140
94.96	0.04	94.55	0.05	92.02	0.06	94.06	0.06			94.13	0.06	96.86	0.00	98.14	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1811755930
95.00	0.04	94.62	0.07	92.13	0.11	94.06	0.00			94.18	0.05	96.86	0.00	98.14	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.100686193
95.04	0.04	94.62	0.01	92.14	0.01	94.07	0.01			94.19	0.01	97.04	0.18	98.16	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.913643606
95.07	0.04	94.62	0.01	92.15	0.01	94.08	0.01			94.20	0.01	97.23	0.18	98.17	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.82703398
95.11	0.04	94.62	0.00	92.37	0.22	94.08	0.00			94.20	0.00	97.23	0.00	98.17	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.3200244158
95.14	0.03	94.64	0.02	92.39	0.02	94.22	0.15			94.22	0.02	97.23	0.00	98.17	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3206735615
95.17	0.03	94.64	0.00	92.39	0.00	94.39	0.17			94.22	0.00	97.23	0.00	98.17	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1268952131
95.20	0.03	94.71	0.07	92.44	0.05	94.39	0.00			94.26	0.03	97.23	0.00	98.17	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.504972757
95.22	0.03	94.78	0.07	92.49	0.05	94.39	0.00			94.29	0.03	97.23	0.00	98.17	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3329488564
95.25	0.02	94.78	0.00	92.63	0.14	94.39	0.00			94.29	0.00	97.23	0.00	98.17	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1066214356
95.27	0.02	94.80	0.02	92.70	0.06	94.39	0.01			94.34	0.05	97.23	0.00	98.17	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.4276372646
95.29	0.02	94.80	0.00	92.78	0.09	94.39	0.00			94.37	0.03	97.23	0.00	98.18	0.01	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1250718248
95.31	0.02	94.80	0.00	92.81	0.03	94.39	0.00			94.39	0.02	97.23	0.00	98.26	0.08	/workspace/coverage/cover_reg_top/29.xbar_stress_all.908276793
95.33	0.02	94.80	0.00	92.88	0.06	94.39	0.00			94.39	0.00	97.23	0.00	98.31	0.05	/workspace/coverage/cover_reg_top/0.xbar_stress_all.3288044
95.35	0.02	94.80	0.00	92.88	0.00	94.39	0.00			94.39	0.00	97.23	0.00	98.41	0.11	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1003396521
95.37	0.02	94.80	0.00	92.88	0.00	94.49	0.10			94.39	0.00	97.23	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1272657769
95.38	0.02	94.80	0.00	92.97	0.09	94.49	0.00			94.39	0.00	97.23	0.00	98.43	0.01	/workspace/coverage/cover_reg_top/2.chip_tl_errors.2383473911
95.40	0.02	94.80	0.00	93.07	0.10	94.49	0.00			94.39	0.00	97.23	0.00	98.43	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2596889372
95.42	0.02	94.80	0.00	93.07	0.00	94.49	0.00			94.39	0.00	97.23	0.00	98.52	0.09	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2160172095
95.43	0.01	94.80	0.00	93.07	0.00	94.58	0.09			94.39	0.00	97.23	0.00	98.52	0.00	/workspace/coverage/default/1.chip_sw_flash_init.3239984566
95.44	0.01	94.83	0.03	93.08	0.01	94.58	0.01			94.40	0.01	97.23	0.00	98.53	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1332694956
95.45	0.01	94.83	0.00	93.08	0.00	94.58	0.00			94.40	0.00	97.23	0.00	98.60	0.07	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3439560213
95.46	0.01	94.83	0.00	93.14	0.06	94.58	0.00			94.40	0.00	97.23	0.00	98.60	0.00	/workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.975979356
95.47	0.01	94.85	0.03	93.15	0.01	94.59	0.01			94.41	0.02	97.23	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3924961491
95.48	0.01	94.85	0.00	93.20	0.05	94.59	0.00			94.41	0.00	97.23	0.00	98.60	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3035011866
95.49	0.01	94.88	0.03	93.21	0.01	94.59	0.01			94.43	0.02	97.23	0.00	98.60	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.887209372
95.50	0.01	94.90	0.02	93.21	0.01	94.60	0.01			94.45	0.02	97.23	0.00	98.60	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.364990613
95.51	0.01	94.90	0.00	93.27	0.05	94.60	0.00			94.45	0.00	97.23	0.00	98.60	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2135953342
95.52	0.01	94.90	0.00	93.28	0.01	94.60	0.00			94.45	0.00	97.23	0.00	98.64	0.04	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.66051016
95.52	0.01	94.90	0.00	93.29	0.01	94.60	0.00			94.45	0.00	97.23	0.00	98.67	0.04	/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2711560663
95.53	0.01	94.90	0.00	93.31	0.02	94.60	0.00			94.45	0.00	97.23	0.00	98.70	0.02	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.925573414
95.54	0.01	94.90	0.00	93.31	0.00	94.65	0.04			94.45	0.00	97.23	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2538845318
95.54	0.01	94.90	0.00	93.36	0.04	94.65	0.00			94.45	0.00	97.23	0.00	98.70	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.174570249
95.55	0.01	94.90	0.00	93.40	0.04	94.65	0.00			94.45	0.00	97.23	0.00	98.70	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1799009271
95.56	0.01	94.90	0.00	93.41	0.01	94.67	0.03			94.45	0.00	97.23	0.00	98.70	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1367563634
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95.78	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.53	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.1144625711
95.78	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.54	0.01	/workspace/coverage/default/70.chip_sw_all_escalation_resets.806005030
95.79	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.55	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3123022830
95.79	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.57	0.01	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2266962468
95.79	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.58	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.3808137245
95.79	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.59	0.01	/workspace/coverage/default/77.chip_sw_all_escalation_resets.714042657
95.79	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.60	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2658198841
95.80	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.61	0.01	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600528516
95.80	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.62	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2803071214
95.80	0.01	94.97	0.00	93.62	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.64	0.01	/workspace/coverage/default/96.chip_sw_all_escalation_resets.2708881030
95.80	0.01	94.97	0.00	93.63	0.01	94.88	0.00			94.46	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4022949562
95.80	0.01	94.97	0.00	93.64	0.01	94.88	0.00			94.46	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.120717095
95.81	0.01	94.97	0.01	93.65	0.01	94.88	0.00			94.46	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2701320103
95.81	0.01	94.99	0.01	93.65	0.00	94.88	0.00			94.46	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.117689332
95.81	0.01	94.99	0.01	93.65	0.00	94.89	0.01			94.46	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/41.chip_sw_all_escalation_resets.357624332
95.81	0.01	94.99	0.00	93.65	0.01	94.89	0.01			94.46	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1910514629
95.81	0.01	94.99	0.00	93.65	0.00	94.90	0.01			94.46	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3381238878
95.81	0.01	94.99	0.00	93.65	0.00	94.91	0.01			94.46	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2007453921
95.82	0.01	94.99	0.00	93.66	0.01	94.92	0.01			94.46	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc.1352562419
95.82	0.01	94.99	0.00	93.66	0.00	94.92	0.00			94.47	0.01	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3369715900
95.82	0.01	94.99	0.00	93.66	0.00	94.92	0.00			94.48	0.01	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.1236122440
95.82	0.01	94.99	0.00	93.67	0.01	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3520707498
95.82	0.01	94.99	0.00	93.67	0.01	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1309531732
95.82	0.01	94.99	0.00	93.68	0.01	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all.2672272923
95.82	0.01	94.99	0.00	93.69	0.01	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1379961146
95.82	0.01	94.99	0.00	93.69	0.01	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3100764205
95.83	0.01	94.99	0.00	93.70	0.01	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.1182895461
95.83	0.01	94.99	0.00	93.71	0.01	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/2.chip_sw_gpio.810171948
95.83	0.01	94.99	0.01	93.71	0.01	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_rw.3273007121
95.83	0.01	95.00	0.01	93.71	0.00	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3228963066
95.83	0.01	95.01	0.01	93.71	0.00	94.92	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1071655184
95.83	0.01	95.01	0.00	93.71	0.00	94.92	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1774863664
95.83	0.01	95.01	0.00	93.71	0.00	94.93	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1871728045
95.83	0.01	95.01	0.00	93.71	0.00	94.94	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.216081864
95.83	0.01	95.01	0.00	93.72	0.01	94.94	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1296698728
95.83	0.01	95.01	0.00	93.72	0.00	94.94	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3857655213
95.84	0.01	95.01	0.00	93.72	0.00	94.95	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.349109471
95.84	0.01	95.01	0.00	93.72	0.00	94.95	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2341217476
95.84	0.01	95.01	0.00	93.72	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.3124778531
95.84	0.01	95.01	0.00	93.72	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/14.xbar_error_random.322941750
95.84	0.01	95.01	0.00	93.73	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1482917397
95.84	0.01	95.01	0.00	93.73	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/25.xbar_access_same_device.289145480
95.84	0.01	95.01	0.00	93.73	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1799902205
95.84	0.01	95.01	0.00	93.74	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.661473319
95.84	0.01	95.01	0.00	93.74	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.986482626
95.84	0.01	95.01	0.00	93.74	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.3794897720
95.84	0.01	95.01	0.00	93.75	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/6.chip_tl_errors.131467698
95.84	0.01	95.01	0.00	93.75	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.1335223169
95.84	0.01	95.01	0.00	93.76	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.595780604
95.84	0.01	95.01	0.00	93.76	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2995666654
95.84	0.01	95.01	0.00	93.76	0.01	94.95	0.00			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3536986171
95.84	0.01	95.01	0.00	93.76	0.00	94.96	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3018906691
95.85	0.01	95.01	0.00	93.76	0.00	94.96	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2959345998
95.85	0.01	95.01	0.00	93.76	0.00	94.96	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2636173881
95.85	0.01	95.01	0.00	93.76	0.00	94.96	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3987203591
95.85	0.01	95.01	0.00	93.76	0.00	94.97	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2513686031
95.85	0.01	95.01	0.00	93.76	0.00	94.97	0.01			94.48	0.00	97.23	0.00	99.64	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2406803075

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2729724591
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2481591479
/workspace/coverage/cover_reg_top/0.chip_csr_rw.423762364
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4089494928
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2246835869
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1463179999
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3456433384
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3492283718
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.4150798928
/workspace/coverage/cover_reg_top/0.xbar_error_random.2401671347
/workspace/coverage/cover_reg_top/0.xbar_random.4044189592
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2552159261
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2112300129
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.174063653
/workspace/coverage/cover_reg_top/0.xbar_same_source.3061192373
/workspace/coverage/cover_reg_top/0.xbar_smoke.2263155164
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.668514534
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.487619563
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2413807671
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.906797899
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4131105882
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2108475524
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2626881031
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4091869237
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2008309743
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2274122025
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2017575977
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2976567787
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1564403362
/workspace/coverage/cover_reg_top/1.chip_tl_errors.824396459
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1802962833
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2542629353
/workspace/coverage/cover_reg_top/1.xbar_error_random.624105077
/workspace/coverage/cover_reg_top/1.xbar_random.1535127639
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2868504563
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.949582868
/workspace/coverage/cover_reg_top/1.xbar_same_source.3832953079
/workspace/coverage/cover_reg_top/1.xbar_smoke.147178515
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3942212931
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3894156187
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3399699028
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2304084521
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.287983950
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1241859647
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3046431905
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1879919669
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3462985858
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2065903185
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.4052066449
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2221740453
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3709355441
/workspace/coverage/cover_reg_top/10.xbar_error_random.3333094464
/workspace/coverage/cover_reg_top/10.xbar_random.1277710536
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3719603456
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.4115256107
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1980016131
/workspace/coverage/cover_reg_top/10.xbar_same_source.4211964432
/workspace/coverage/cover_reg_top/10.xbar_smoke.950061846
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.4152566905
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.37787397
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3708566551
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3751814016
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.765442817
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3643397434
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3673592962
/workspace/coverage/cover_reg_top/11.chip_csr_rw.367982452
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.699344880
/workspace/coverage/cover_reg_top/11.chip_tl_errors.2244795789
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2863438351
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3315539179
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1576099466
/workspace/coverage/cover_reg_top/11.xbar_error_random.3929865233
/workspace/coverage/cover_reg_top/11.xbar_random.1317271087
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.863849202
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.769281013
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2899288831
/workspace/coverage/cover_reg_top/11.xbar_same_source.2286116848
/workspace/coverage/cover_reg_top/11.xbar_smoke.4132356333
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1926695296
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3602374287
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4266931616
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1303787780
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2377040901
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1754200392
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3694494015
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2569799178
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3905691823
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1792525944
/workspace/coverage/cover_reg_top/12.chip_tl_errors.424736976
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3769305492
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2015515624
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1646904669
/workspace/coverage/cover_reg_top/12.xbar_error_random.2463795617
/workspace/coverage/cover_reg_top/12.xbar_random.1750200590
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3501845188
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2891927484
/workspace/coverage/cover_reg_top/12.xbar_same_source.204571853
/workspace/coverage/cover_reg_top/12.xbar_smoke.3789388280
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2059197486
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/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2886814462
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3207831484
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2368276437
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2790174982
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2118664784
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2257227967
/workspace/coverage/default/3.chip_tap_straps_dev.3596427456
/workspace/coverage/default/3.chip_tap_straps_prod.3829442165
/workspace/coverage/default/3.chip_tap_straps_rma.2294476229
/workspace/coverage/default/3.chip_tap_straps_testunlock0.687080852
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.439070460
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2464026101
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879945845
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1782100083
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2551048381
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2336867618
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1420457343
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.360921551
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134459871
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2668818396
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1852272797
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3552948524
/workspace/coverage/default/39.chip_sw_all_escalation_resets.95924783
/workspace/coverage/default/4.chip_sw_all_escalation_resets.10861513
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1385076313
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.67617710
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.398435794
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2510599718
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.507412436
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3976663059
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2994423702
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.829357760
/workspace/coverage/default/4.chip_tap_straps_dev.617843223
/workspace/coverage/default/4.chip_tap_straps_prod.1910725010
/workspace/coverage/default/4.chip_tap_straps_rma.3295137120
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2813331958
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3608320751
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3803083113
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4264824440
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1167844079
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.237328907
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1350328988
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1564393702
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771485533
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2762696558
/workspace/coverage/default/47.chip_sw_all_escalation_resets.4028627294
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1697535120
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2145025277
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1887847400
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.27243636
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.357561966
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3688892092
/workspace/coverage/default/50.chip_sw_all_escalation_resets.936284290
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2770849473
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2708843850
/workspace/coverage/default/53.chip_sw_all_escalation_resets.674280362
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.410767420
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1390738191
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1546532797
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2333373520
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2919442048
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3663131238
/workspace/coverage/default/59.chip_sw_all_escalation_resets.56504443
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029471557
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1196846966
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3547721548
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1019278588
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1245021063
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.868741428
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2998694882
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.15291180
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3677758501
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878556365
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1824041586
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1042046554
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2738244524
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1556342879
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1489939209
/workspace/coverage/default/69.chip_sw_all_escalation_resets.615307062
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.346438531
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1870419648
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2627167044
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3949557948
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3775529541
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1210800889
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2103650857
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2047601253
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2471300602
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1605963551
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2698594110
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3131093546
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.592623691
/workspace/coverage/default/78.chip_sw_all_escalation_resets.922845942
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2591699005
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1493043349
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3327249655
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2423053108
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1782518089
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.350363068
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1403075004
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278902015
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2576119121
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.275135830
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1450024980
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2781829361
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3010485207
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227081772
/workspace/coverage/default/84.chip_sw_all_escalation_resets.674490856
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1301751206
/workspace/coverage/default/86.chip_sw_all_escalation_resets.984846024
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.306643425
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1706881294
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1106483977
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3244704476
/workspace/coverage/default/89.chip_sw_all_escalation_resets.917639487
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761985471
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2720753956
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1084809439
/workspace/coverage/default/90.chip_sw_all_escalation_resets.136218284
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1778743123
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1558964621
/workspace/coverage/default/93.chip_sw_all_escalation_resets.4064038701
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2104496743
/workspace/coverage/default/95.chip_sw_all_escalation_resets.612250661
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3074792007
/workspace/coverage/default/98.chip_sw_all_escalation_resets.17065291
/workspace/coverage/default/99.chip_sw_all_escalation_resets.861887390
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.192770014
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1245052626
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1466163653
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3254487869
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2468793976
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1196570800
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2823079949
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3170043260

---

Total test records in report: 2823

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1865044205			Mar 19 03:46:34 PM PDT 24	Mar 19 05:24:04 PM PDT 24	47957324296 ps
T2	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2905396902			Mar 19 03:57:33 PM PDT 24	Mar 19 04:33:25 PM PDT 24	8227360000 ps
T3	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3349461823			Mar 19 04:05:01 PM PDT 24	Mar 19 04:09:04 PM PDT 24	2652237572 ps
T4	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3688892092			Mar 19 04:08:58 PM PDT 24	Mar 19 04:19:02 PM PDT 24	7719627862 ps
T29	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1626278086			Mar 19 03:53:20 PM PDT 24	Mar 19 04:19:46 PM PDT 24	14261396047 ps
T51	/workspace/coverage/default/1.chip_sw_otbn_randomness.904559166			Mar 19 03:48:18 PM PDT 24	Mar 19 04:02:55 PM PDT 24	5872389450 ps
T52	/workspace/coverage/default/56.chip_sw_all_escalation_resets.1056696334			Mar 19 04:12:40 PM PDT 24	Mar 19 04:23:19 PM PDT 24	5174216444 ps
T78	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1338903923			Mar 19 03:44:43 PM PDT 24	Mar 19 03:48:35 PM PDT 24	2882174120 ps
T79	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1811755930			Mar 19 03:47:44 PM PDT 24	Mar 19 03:55:08 PM PDT 24	4636421776 ps
T80	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3042571550			Mar 19 03:51:26 PM PDT 24	Mar 19 04:11:46 PM PDT 24	5303533404 ps
T56	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1663177834			Mar 19 03:50:15 PM PDT 24	Mar 19 04:21:31 PM PDT 24	11853006024 ps
T39	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2307978493			Mar 19 03:47:56 PM PDT 24	Mar 19 03:59:49 PM PDT 24	3819882264 ps
T103	/workspace/coverage/default/1.chip_sw_otbn_smoketest.2773464769			Mar 19 03:53:42 PM PDT 24	Mar 19 04:24:16 PM PDT 24	8442647870 ps
T271	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.136853954			Mar 19 03:58:33 PM PDT 24	Mar 19 04:04:01 PM PDT 24	2620744936 ps
T176	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1261396225			Mar 19 03:52:04 PM PDT 24	Mar 19 04:03:46 PM PDT 24	6020649336 ps
T152	/workspace/coverage/default/1.chip_sw_edn_boot_mode.1912058032			Mar 19 03:50:32 PM PDT 24	Mar 19 04:00:31 PM PDT 24	3017189532 ps
T196	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2210596516			Mar 19 03:51:13 PM PDT 24	Mar 19 04:06:01 PM PDT 24	5934623882 ps
T130	/workspace/coverage/default/26.chip_sw_all_escalation_resets.298422755			Mar 19 04:08:01 PM PDT 24	Mar 19 04:18:33 PM PDT 24	4881605272 ps
T177	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1332694956			Mar 19 04:11:42 PM PDT 24	Mar 19 04:23:25 PM PDT 24	5735234352 ps
T14	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1738923685			Mar 19 03:46:35 PM PDT 24	Mar 19 03:54:30 PM PDT 24	4032472870 ps
T35	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2539724502			Mar 19 03:59:29 PM PDT 24	Mar 19 04:49:01 PM PDT 24	12523089810 ps
T18	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4055266013			Mar 19 03:58:59 PM PDT 24	Mar 19 04:59:47 PM PDT 24	20184766620 ps
T108	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1871728045			Mar 19 03:48:48 PM PDT 24	Mar 19 04:01:18 PM PDT 24	4551068992 ps
T37	/workspace/coverage/default/0.rom_e2e_asm_init_rma.1182108215			Mar 19 03:51:12 PM PDT 24	Mar 19 04:28:39 PM PDT 24	8792280357 ps
T153	/workspace/coverage/default/1.chip_sw_edn_kat.560140908			Mar 19 03:48:13 PM PDT 24	Mar 19 03:57:42 PM PDT 24	3569094168 ps
T881	/workspace/coverage/default/2.chip_sw_example_concurrency.2661903462			Mar 19 03:55:39 PM PDT 24	Mar 19 04:00:38 PM PDT 24	2578468254 ps
T131	/workspace/coverage/default/7.chip_sw_all_escalation_resets.1144625711			Mar 19 04:06:19 PM PDT 24	Mar 19 04:16:52 PM PDT 24	5913356650 ps
T327	/workspace/coverage/default/87.chip_sw_all_escalation_resets.1706881294			Mar 19 04:12:43 PM PDT 24	Mar 19 04:20:29 PM PDT 24	4824319200 ps
T38	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1272657769			Mar 19 03:46:14 PM PDT 24	Mar 19 03:49:09 PM PDT 24	2899028040 ps
T104	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4090868663			Mar 19 03:59:16 PM PDT 24	Mar 19 04:59:49 PM PDT 24	16791215276 ps
T15	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3206735615			Mar 19 03:46:20 PM PDT 24	Mar 19 05:43:30 PM PDT 24	31128054254 ps
T291	/workspace/coverage/default/1.chip_sw_hmac_enc.1352562419			Mar 19 03:50:16 PM PDT 24	Mar 19 03:54:20 PM PDT 24	2951067368 ps
T216	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3618553775			Mar 19 03:58:20 PM PDT 24	Mar 19 04:21:40 PM PDT 24	10997242525 ps
T202	/workspace/coverage/default/75.chip_sw_all_escalation_resets.2698594110			Mar 19 04:12:34 PM PDT 24	Mar 19 04:21:38 PM PDT 24	4767623994 ps
T144	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2900085560			Mar 19 04:02:17 PM PDT 24	Mar 19 04:14:20 PM PDT 24	5156463733 ps
T214	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3807994787			Mar 19 03:52:01 PM PDT 24	Mar 19 03:56:28 PM PDT 24	2938273560 ps
T882	/workspace/coverage/default/2.chip_sw_csrng_kat_test.3056155071			Mar 19 03:59:59 PM PDT 24	Mar 19 04:03:16 PM PDT 24	2416484184 ps
T656	/workspace/coverage/default/1.chip_sw_edn_sw_mode.1945265275			Mar 19 03:46:03 PM PDT 24	Mar 19 04:22:43 PM PDT 24	9944657390 ps
T11	/workspace/coverage/default/0.chip_sw_gpio_smoketest.1400091925			Mar 19 03:48:58 PM PDT 24	Mar 19 03:53:06 PM PDT 24	3355159943 ps
T123	/workspace/coverage/default/1.chip_sw_flash_init.3239984566			Mar 19 03:48:30 PM PDT 24	Mar 19 04:24:22 PM PDT 24	19903561294 ps
T189	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.829357760			Mar 19 04:08:23 PM PDT 24	Mar 19 04:22:52 PM PDT 24	5133634576 ps
T36	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1450526785			Mar 19 03:52:18 PM PDT 24	Mar 19 04:21:35 PM PDT 24	8072916664 ps
T215	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.61716131			Mar 19 03:48:23 PM PDT 24	Mar 19 03:52:50 PM PDT 24	2495374760 ps
T697	/workspace/coverage/default/2.chip_sw_aes_idle.3570430788			Mar 19 03:59:02 PM PDT 24	Mar 19 04:03:55 PM PDT 24	3029543862 ps
T115	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2886814462			Mar 19 04:06:00 PM PDT 24	Mar 19 04:15:24 PM PDT 24	7728242600 ps
T303	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3533334859			Mar 19 03:49:07 PM PDT 24	Mar 19 03:53:21 PM PDT 24	2518239304 ps
T305	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1061922598			Mar 19 04:12:00 PM PDT 24	Mar 19 04:17:33 PM PDT 24	2882240892 ps
T125	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1764979791			Mar 19 03:55:49 PM PDT 24	Mar 19 04:22:57 PM PDT 24	8390249050 ps
T199	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1790506647			Mar 19 04:03:27 PM PDT 24	Mar 19 04:37:08 PM PDT 24	24626136568 ps
T179	/workspace/coverage/default/1.chip_sw_power_idle_load.42589494			Mar 19 03:51:27 PM PDT 24	Mar 19 04:03:43 PM PDT 24	3936161958 ps
T60	/workspace/coverage/default/1.rom_raw_unlock.3256454479			Mar 19 03:50:29 PM PDT 24	Mar 19 04:21:46 PM PDT 24	15413603032 ps
T306	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607558327			Mar 19 04:09:56 PM PDT 24	Mar 19 04:16:59 PM PDT 24	3888683088 ps
T135	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.4212225778			Mar 19 03:50:40 PM PDT 24	Mar 19 03:54:38 PM PDT 24	2554797580 ps
T248	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.65191108			Mar 19 03:51:40 PM PDT 24	Mar 19 04:18:36 PM PDT 24	12631761392 ps
T57	/workspace/coverage/default/2.chip_tap_straps_testunlock0.771947451			Mar 19 04:03:04 PM PDT 24	Mar 19 04:06:58 PM PDT 24	3059066383 ps
T145	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1845962286			Mar 19 03:47:11 PM PDT 24	Mar 19 03:51:42 PM PDT 24	3023876106 ps
T149	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.842680611			Mar 19 03:46:42 PM PDT 24	Mar 19 04:15:52 PM PDT 24	13413177346 ps
T249	/workspace/coverage/default/0.chip_sw_aes_enc.2030059720			Mar 19 03:50:18 PM PDT 24	Mar 19 03:54:57 PM PDT 24	2692649152 ps
T250	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.410767420			Mar 19 04:10:35 PM PDT 24	Mar 19 04:16:17 PM PDT 24	3041546456 ps
T187	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.94257782			Mar 19 03:47:59 PM PDT 24	Mar 19 03:51:42 PM PDT 24	2523236358 ps
T251	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278902015			Mar 19 04:13:03 PM PDT 24	Mar 19 04:19:13 PM PDT 24	3994816800 ps
T252	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2006718472			Mar 19 03:52:33 PM PDT 24	Mar 19 03:58:07 PM PDT 24	3404182928 ps
T658	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.306643425			Mar 19 04:13:47 PM PDT 24	Mar 19 04:19:42 PM PDT 24	3974167560 ps
T317	/workspace/coverage/default/45.chip_sw_all_escalation_resets.1098312095			Mar 19 04:10:01 PM PDT 24	Mar 19 04:20:55 PM PDT 24	4903978478 ps
T178	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3359027161			Mar 19 03:51:08 PM PDT 24	Mar 19 04:04:01 PM PDT 24	5667425355 ps
T146	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3195425374			Mar 19 03:49:18 PM PDT 24	Mar 19 03:58:45 PM PDT 24	4574638944 ps
T679	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2591699005			Mar 19 04:12:52 PM PDT 24	Mar 19 04:19:19 PM PDT 24	3670886342 ps
T315	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1493043349			Mar 19 04:14:50 PM PDT 24	Mar 19 04:26:22 PM PDT 24	6043448798 ps
T883	/workspace/coverage/default/0.chip_sw_example_flash.1166445821			Mar 19 03:47:52 PM PDT 24	Mar 19 03:51:57 PM PDT 24	3249514540 ps
T675	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761985471			Mar 19 04:09:06 PM PDT 24	Mar 19 04:16:42 PM PDT 24	3458047404 ps
T203	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2635242837			Mar 19 03:48:47 PM PDT 24	Mar 19 03:57:29 PM PDT 24	5360939656 ps
T154	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1367563634			Mar 19 03:52:24 PM PDT 24	Mar 19 04:16:41 PM PDT 24	6287083060 ps
T8	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3072607457			Mar 19 03:47:30 PM PDT 24	Mar 19 03:56:00 PM PDT 24	5564634611 ps
T225	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2593263020			Mar 19 03:58:46 PM PDT 24	Mar 19 04:40:06 PM PDT 24	37781391570 ps
T132	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4206397167			Mar 19 03:44:38 PM PDT 24	Mar 19 03:57:39 PM PDT 24	5379048626 ps
T105	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1813736288			Mar 19 03:51:13 PM PDT 24	Mar 19 04:55:30 PM PDT 24	24117217368 ps
T114	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2777950485			Mar 19 04:08:02 PM PDT 24	Mar 19 04:17:37 PM PDT 24	4306771792 ps
T226	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.505530379			Mar 19 03:48:17 PM PDT 24	Mar 19 03:57:19 PM PDT 24	4672958220 ps
T227	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4097503464			Mar 19 03:50:53 PM PDT 24	Mar 19 03:58:54 PM PDT 24	5280622736 ps
T228	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.95350354			Mar 19 03:57:20 PM PDT 24	Mar 19 04:33:03 PM PDT 24	7066756226 ps
T884	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2277552040			Mar 19 03:45:23 PM PDT 24	Mar 19 04:04:19 PM PDT 24	8157624080 ps
T349	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1902922675			Mar 19 03:52:32 PM PDT 24	Mar 19 04:39:03 PM PDT 24	9363147188 ps
T677	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.868741428			Mar 19 04:11:20 PM PDT 24	Mar 19 04:18:40 PM PDT 24	3869455654 ps
T676	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1367256337			Mar 19 04:08:19 PM PDT 24	Mar 19 04:21:50 PM PDT 24	6336455780 ps
T885	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.700417239			Mar 19 03:50:32 PM PDT 24	Mar 19 03:59:01 PM PDT 24	4203087794 ps
T886	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.196538102			Mar 19 03:48:07 PM PDT 24	Mar 19 03:55:37 PM PDT 24	3582442912 ps
T142	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2295587706			Mar 19 03:53:17 PM PDT 24	Mar 19 04:53:29 PM PDT 24	18574625425 ps
T887	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1808830995			Mar 19 03:56:47 PM PDT 24	Mar 19 04:02:14 PM PDT 24	3917540140 ps
T126	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2439849393			Mar 19 03:47:34 PM PDT 24	Mar 19 04:00:42 PM PDT 24	9707147853 ps
T136	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2281916000			Mar 19 03:51:20 PM PDT 24	Mar 19 03:57:24 PM PDT 24	2784877710 ps
T354	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.487085725			Mar 19 04:14:36 PM PDT 24	Mar 19 04:21:39 PM PDT 24	3382821586 ps
T346	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1824041586			Mar 19 04:11:17 PM PDT 24	Mar 19 04:17:38 PM PDT 24	3753154504 ps
T355	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.349109471			Mar 19 03:48:19 PM PDT 24	Mar 19 04:06:05 PM PDT 24	6934095754 ps
T12	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.507412436			Mar 19 04:07:41 PM PDT 24	Mar 19 04:22:49 PM PDT 24	6349360195 ps
T356	/workspace/coverage/default/5.chip_sw_all_escalation_resets.580771650			Mar 19 04:05:25 PM PDT 24	Mar 19 04:19:46 PM PDT 24	5403400968 ps
T122	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2442340893			Mar 19 03:53:02 PM PDT 24	Mar 19 05:27:16 PM PDT 24	47777117505 ps
T338	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2642541140			Mar 19 04:08:42 PM PDT 24	Mar 19 04:16:28 PM PDT 24	4199413744 ps
T182	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3343357802			Mar 19 04:01:21 PM PDT 24	Mar 19 04:07:12 PM PDT 24	3282858522 ps
T133	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4040027001			Mar 19 03:56:03 PM PDT 24	Mar 19 04:05:22 PM PDT 24	5040044620 ps
T260	/workspace/coverage/default/0.rom_keymgr_functest.2793417754			Mar 19 03:51:55 PM PDT 24	Mar 19 04:01:36 PM PDT 24	5586323760 ps
T192	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.978178037			Mar 19 03:49:13 PM PDT 24	Mar 19 04:12:32 PM PDT 24	8465165848 ps
T124	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2743985363			Mar 19 03:56:30 PM PDT 24	Mar 19 05:25:45 PM PDT 24	47518537034 ps
T348	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2282430412			Mar 19 03:49:47 PM PDT 24	Mar 19 03:55:47 PM PDT 24	3456705568 ps
T255	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1603184454			Mar 19 04:02:50 PM PDT 24	Mar 19 04:12:11 PM PDT 24	4961425656 ps
T267	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1268952131			Mar 19 03:53:47 PM PDT 24	Mar 19 04:03:52 PM PDT 24	4924118550 ps
T299	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2790174982			Mar 19 04:05:43 PM PDT 24	Mar 19 04:14:17 PM PDT 24	5146253479 ps
T127	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2805546170			Mar 19 03:47:19 PM PDT 24	Mar 19 03:50:08 PM PDT 24	3561827788 ps
T197	/workspace/coverage/default/2.chip_sw_uart_tx_rx.2821183968			Mar 19 03:53:56 PM PDT 24	Mar 19 04:07:16 PM PDT 24	5176627490 ps
T256	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3611585718			Mar 19 03:47:40 PM PDT 24	Mar 19 03:57:29 PM PDT 24	4087741622 ps
T270	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3693491930			Mar 19 03:46:56 PM PDT 24	Mar 19 04:12:15 PM PDT 24	8299934854 ps
T399	/workspace/coverage/default/0.chip_sw_kmac_smoketest.2430367773			Mar 19 03:46:43 PM PDT 24	Mar 19 03:50:30 PM PDT 24	3401202936 ps
T888	/workspace/coverage/default/0.chip_sw_otbn_randomness.484860311			Mar 19 03:49:28 PM PDT 24	Mar 19 04:07:38 PM PDT 24	5374549496 ps
T756	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2658198841			Mar 19 04:13:57 PM PDT 24	Mar 19 04:21:45 PM PDT 24	3453294000 ps
T61	/workspace/coverage/default/2.chip_jtag_mem_access.2842384370			Mar 19 03:55:13 PM PDT 24	Mar 19 04:19:47 PM PDT 24	13087974896 ps
T9	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3195581378			Mar 19 03:45:21 PM PDT 24	Mar 19 03:50:25 PM PDT 24	3587009984 ps
T364	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3663184833			Mar 19 03:58:08 PM PDT 24	Mar 19 04:36:25 PM PDT 24	9193604718 ps
T889	/workspace/coverage/default/2.chip_sw_aes_smoketest.1392366742			Mar 19 04:05:20 PM PDT 24	Mar 19 04:10:38 PM PDT 24	2707755200 ps
T211	/workspace/coverage/default/2.chip_sw_plic_sw_irq.964580589			Mar 19 04:03:20 PM PDT 24	Mar 19 04:08:27 PM PDT 24	2428694520 ps
T206	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3369715900			Mar 19 03:46:23 PM PDT 24	Mar 19 03:54:09 PM PDT 24	4870805140 ps
T330	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3685080779			Mar 19 03:47:51 PM PDT 24	Mar 19 03:55:20 PM PDT 24	3456787992 ps
T128	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2027619386			Mar 19 03:50:38 PM PDT 24	Mar 19 04:23:32 PM PDT 24	31951070155 ps
T162	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3924961491			Mar 19 03:47:00 PM PDT 24	Mar 19 03:58:31 PM PDT 24	5746341318 ps
T341	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3406372886			Mar 19 03:57:56 PM PDT 24	Mar 19 04:37:10 PM PDT 24	21984182163 ps
T229	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.879071927			Mar 19 03:57:10 PM PDT 24	Mar 19 03:59:06 PM PDT 24	2826831016 ps
T342	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3766671697			Mar 19 03:47:38 PM PDT 24	Mar 19 03:58:32 PM PDT 24	4717273452 ps
T143	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2011535913			Mar 19 03:50:02 PM PDT 24	Mar 19 04:08:33 PM PDT 24	5151818788 ps
T318	/workspace/coverage/default/67.chip_sw_all_escalation_resets.2738244524			Mar 19 04:11:03 PM PDT 24	Mar 19 04:18:36 PM PDT 24	4357424312 ps
T134	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2471231371			Mar 19 03:57:51 PM PDT 24	Mar 19 04:07:27 PM PDT 24	8011689756 ps
T188	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.996703252			Mar 19 03:50:27 PM PDT 24	Mar 19 04:01:37 PM PDT 24	4713408701 ps
T129	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.332377571			Mar 19 03:48:34 PM PDT 24	Mar 19 03:51:14 PM PDT 24	2891383973 ps
T343	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134459871			Mar 19 04:11:53 PM PDT 24	Mar 19 04:17:42 PM PDT 24	4369311320 ps
T183	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3758657462			Mar 19 04:06:28 PM PDT 24	Mar 19 04:14:40 PM PDT 24	4286005960 ps
T350	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1296698728			Mar 19 03:54:51 PM PDT 24	Mar 19 04:51:23 PM PDT 24	11488538592 ps
T184	/workspace/coverage/default/55.chip_sw_all_escalation_resets.1390738191			Mar 19 04:13:19 PM PDT 24	Mar 19 04:23:50 PM PDT 24	4369107112 ps
T890	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1708153460			Mar 19 03:49:05 PM PDT 24	Mar 19 03:59:55 PM PDT 24	4423368250 ps
T891	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.343306165			Mar 19 03:58:30 PM PDT 24	Mar 19 04:06:01 PM PDT 24	4922748040 ps
T400	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.930119388			Mar 19 04:04:55 PM PDT 24	Mar 19 04:11:41 PM PDT 24	3086894864 ps
T678	/workspace/coverage/default/0.chip_sw_all_escalation_resets.152180709			Mar 19 03:48:38 PM PDT 24	Mar 19 04:00:18 PM PDT 24	3915540750 ps
T892	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.808317907			Mar 19 03:51:07 PM PDT 24	Mar 19 04:22:58 PM PDT 24	34313899922 ps
T231	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.67617710			Mar 19 04:06:24 PM PDT 24	Mar 19 04:16:33 PM PDT 24	5092452540 ps
T139	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2004711963			Mar 19 03:49:42 PM PDT 24	Mar 19 04:38:32 PM PDT 24	14285375916 ps
T53	/workspace/coverage/default/1.chip_sw_alert_test.380645063			Mar 19 03:52:17 PM PDT 24	Mar 19 03:57:38 PM PDT 24	2987582524 ps
T893	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1782518089			Mar 19 04:07:28 PM PDT 24	Mar 19 04:27:09 PM PDT 24	11861589274 ps
T359	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1106483977			Mar 19 04:13:37 PM PDT 24	Mar 19 04:21:13 PM PDT 24	3868169324 ps
T308	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1648561175			Mar 19 03:48:23 PM PDT 24	Mar 19 04:03:55 PM PDT 24	4984829575 ps
T796	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1489939209			Mar 19 04:12:58 PM PDT 24	Mar 19 04:20:11 PM PDT 24	3669526540 ps
T58	/workspace/coverage/default/0.chip_tap_straps_rma.1304389620			Mar 19 03:44:53 PM PDT 24	Mar 19 03:48:47 PM PDT 24	3074462719 ps
T894	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.424919093			Mar 19 03:45:46 PM PDT 24	Mar 19 03:50:12 PM PDT 24	2779674380 ps
T895	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1757711701			Mar 19 03:49:45 PM PDT 24	Mar 19 03:52:46 PM PDT 24	2597296606 ps
T896	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3405322316			Mar 19 04:02:37 PM PDT 24	Mar 19 04:09:32 PM PDT 24	3847631266 ps
T897	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4156503390			Mar 19 03:59:22 PM PDT 24	Mar 19 04:07:09 PM PDT 24	6946258600 ps
T401	/workspace/coverage/default/1.chip_sw_kmac_idle.180812277			Mar 19 03:53:40 PM PDT 24	Mar 19 03:58:17 PM PDT 24	2813282262 ps
T898	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1724121636			Mar 19 03:45:32 PM PDT 24	Mar 19 03:52:08 PM PDT 24	5938396806 ps
T217	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2636173881			Mar 19 03:46:50 PM PDT 24	Mar 19 04:14:24 PM PDT 24	5876124612 ps
T899	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2838276884			Mar 19 03:49:47 PM PDT 24	Mar 19 03:55:23 PM PDT 24	2262063602 ps
T232	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.357561966			Mar 19 04:06:19 PM PDT 24	Mar 19 04:18:39 PM PDT 24	5076079852 ps
T297	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2479864286			Mar 19 04:00:27 PM PDT 24	Mar 19 04:28:27 PM PDT 24	7854041256 ps
T657	/workspace/coverage/default/0.chip_sw_edn_kat.3141991657			Mar 19 03:47:32 PM PDT 24	Mar 19 03:58:34 PM PDT 24	3434399602 ps
T684	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2389502324			Mar 19 04:09:32 PM PDT 24	Mar 19 04:18:45 PM PDT 24	4292749994 ps
T165	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3476240184			Mar 19 03:51:00 PM PDT 24	Mar 19 03:59:16 PM PDT 24	4079913136 ps
T69	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2358941655			Mar 19 03:50:28 PM PDT 24	Mar 19 03:58:32 PM PDT 24	4445685860 ps
T900	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.818083559			Mar 19 03:43:33 PM PDT 24	Mar 19 04:08:50 PM PDT 24	14552263972 ps
T10	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4259305970			Mar 19 03:56:44 PM PDT 24	Mar 19 04:06:01 PM PDT 24	4279206590 ps
T63	/workspace/coverage/default/4.chip_tap_straps_prod.1910725010			Mar 19 04:07:50 PM PDT 24	Mar 19 04:18:27 PM PDT 24	6502622867 ps
T901	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1117090607			Mar 19 03:47:54 PM PDT 24	Mar 19 04:17:14 PM PDT 24	23040589500 ps
T259	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.667487320			Mar 19 04:00:32 PM PDT 24	Mar 19 04:10:59 PM PDT 24	4771813248 ps
T902	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.246294048			Mar 19 03:48:25 PM PDT 24	Mar 19 03:56:27 PM PDT 24	4935682056 ps
T903	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.398435794			Mar 19 04:07:08 PM PDT 24	Mar 19 04:18:05 PM PDT 24	6445806246 ps
T683	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3798526438			Mar 19 04:11:42 PM PDT 24	Mar 19 04:19:49 PM PDT 24	4407230728 ps
T904	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.404683388			Mar 19 03:49:35 PM PDT 24	Mar 19 04:36:44 PM PDT 24	22557420280 ps
T905	/workspace/coverage/default/2.chip_sw_uart_smoketest.3099767180			Mar 19 04:06:44 PM PDT 24	Mar 19 04:09:45 PM PDT 24	2493397804 ps
T680	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.439070460			Mar 19 04:09:24 PM PDT 24	Mar 19 04:15:55 PM PDT 24	3956464140 ps
T682	/workspace/coverage/default/77.chip_sw_all_escalation_resets.714042657			Mar 19 04:12:51 PM PDT 24	Mar 19 04:24:49 PM PDT 24	5090386862 ps
T316	/workspace/coverage/default/93.chip_sw_all_escalation_resets.4064038701			Mar 19 04:13:40 PM PDT 24	Mar 19 04:23:01 PM PDT 24	3991585428 ps
T906	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.4246847555			Mar 19 04:06:26 PM PDT 24	Mar 19 04:16:59 PM PDT 24	4135517100 ps
T257	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3141275986			Mar 19 03:46:48 PM PDT 24	Mar 19 03:56:14 PM PDT 24	5267832978 ps
T230	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3276826445			Mar 19 03:46:01 PM PDT 24	Mar 19 03:55:15 PM PDT 24	8579058994 ps
T351	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2921676467			Mar 19 03:53:09 PM PDT 24	Mar 19 04:51:22 PM PDT 24	12229049032 ps
T13	/workspace/coverage/default/0.chip_sw_gpio.2139636767			Mar 19 03:46:38 PM PDT 24	Mar 19 03:56:05 PM PDT 24	4312741060 ps
T23	/workspace/coverage/default/1.chip_sw_gpio_smoketest.233642405			Mar 19 03:51:21 PM PDT 24	Mar 19 03:56:09 PM PDT 24	3248012787 ps
T907	/workspace/coverage/default/1.chip_sw_aes_idle.782751204			Mar 19 03:52:19 PM PDT 24	Mar 19 03:57:14 PM PDT 24	2950120590 ps
T150	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2939320085			Mar 19 04:01:08 PM PDT 24	Mar 19 04:11:44 PM PDT 24	4540770940 ps
T908	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.720440989			Mar 19 03:45:40 PM PDT 24	Mar 19 03:54:53 PM PDT 24	6256112250 ps
T909	/workspace/coverage/default/2.chip_sw_kmac_smoketest.2517177142			Mar 19 04:05:50 PM PDT 24	Mar 19 04:09:34 PM PDT 24	2375329346 ps
T138	/workspace/coverage/default/2.chip_sw_power_sleep_load.727125604			Mar 19 04:03:52 PM PDT 24	Mar 19 04:11:04 PM PDT 24	10120247054 ps
T910	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.273731007			Mar 19 03:56:01 PM PDT 24	Mar 19 04:27:19 PM PDT 24	6955921752 ps
T322	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1497388291			Mar 19 03:51:15 PM PDT 24	Mar 19 03:54:58 PM PDT 24	3026561059 ps
T911	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3169178526			Mar 19 03:53:12 PM PDT 24	Mar 19 03:59:43 PM PDT 24	5051766640 ps
T331	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1910514629			Mar 19 03:46:03 PM PDT 24	Mar 19 03:52:33 PM PDT 24	4138761388 ps
T912	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3429638925			Mar 19 03:47:33 PM PDT 24	Mar 19 03:52:31 PM PDT 24	2518806896 ps
T681	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.984683179			Mar 19 03:53:21 PM PDT 24	Mar 19 04:59:23 PM PDT 24	36863127892 ps
T403	/workspace/coverage/default/2.chip_sw_kmac_entropy.345091230			Mar 19 03:57:51 PM PDT 24	Mar 19 04:01:31 PM PDT 24	3249401176 ps
T913	/workspace/coverage/default/1.chip_sw_aes_smoketest.3614873839			Mar 19 03:52:31 PM PDT 24	Mar 19 03:58:26 PM PDT 24	3200499248 ps
T700	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2454156414			Mar 19 03:57:43 PM PDT 24	Mar 19 04:07:28 PM PDT 24	6546116560 ps
T264	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.63100220			Mar 19 03:48:54 PM PDT 24	Mar 19 05:22:51 PM PDT 24	49996007077 ps
T347	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2738996431			Mar 19 03:59:36 PM PDT 24	Mar 19 04:05:53 PM PDT 24	3770352640 ps
T198	/workspace/coverage/default/0.chip_sw_uart_tx_rx.3681408010			Mar 19 03:46:29 PM PDT 24	Mar 19 04:02:44 PM PDT 24	5197893110 ps
T914	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1815296051			Mar 19 03:46:27 PM PDT 24	Mar 19 03:54:30 PM PDT 24	3956406630 ps
T765	/workspace/coverage/default/29.chip_sw_all_escalation_resets.4041627984			Mar 19 04:07:54 PM PDT 24	Mar 19 04:20:43 PM PDT 24	4715331032 ps
T75	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1442203579			Mar 19 03:47:23 PM PDT 24	Mar 19 04:08:44 PM PDT 24	9008464580 ps
T718	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029471557			Mar 19 04:09:04 PM PDT 24	Mar 19 04:14:32 PM PDT 24	3759385938 ps
T76	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2574511674			Mar 19 04:03:25 PM PDT 24	Mar 19 04:09:30 PM PDT 24	3781879497 ps
T915	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1882271808			Mar 19 03:46:07 PM PDT 24	Mar 19 03:54:49 PM PDT 24	3931727390 ps
T916	/workspace/coverage/default/1.chip_sw_hmac_smoketest.3499247405			Mar 19 03:55:13 PM PDT 24	Mar 19 04:00:30 PM PDT 24	2691524970 ps
T917	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3547721548			Mar 19 04:06:07 PM PDT 24	Mar 19 04:22:49 PM PDT 24	10262639936 ps
T200	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1927626678			Mar 19 03:46:57 PM PDT 24	Mar 19 03:51:51 PM PDT 24	2438832012 ps
T294	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1071655184			Mar 19 03:44:49 PM PDT 24	Mar 19 03:57:28 PM PDT 24	5102718886 ps
T151	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2617707751			Mar 19 03:53:41 PM PDT 24	Mar 19 04:07:48 PM PDT 24	3897825910 ps
T918	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2485051948			Mar 19 03:57:23 PM PDT 24	Mar 19 04:14:34 PM PDT 24	6584137527 ps
T272	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878556365			Mar 19 04:11:33 PM PDT 24	Mar 19 04:18:03 PM PDT 24	4011967448 ps
T276	/workspace/coverage/default/70.chip_sw_all_escalation_resets.806005030			Mar 19 04:13:13 PM PDT 24	Mar 19 04:28:14 PM PDT 24	4953626912 ps
T277	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2257227967			Mar 19 04:06:52 PM PDT 24	Mar 19 04:23:13 PM PDT 24	4696616270 ps
T278	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1241297410			Mar 19 04:02:37 PM PDT 24	Mar 19 04:05:48 PM PDT 24	2038048520 ps
T279	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2006224724			Mar 19 03:52:24 PM PDT 24	Mar 19 03:59:25 PM PDT 24	5474898286 ps
T109	/workspace/coverage/default/0.chip_plic_all_irqs_10.705401405			Mar 19 03:48:13 PM PDT 24	Mar 19 03:56:58 PM PDT 24	4224466300 ps
T280	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3509019053			Mar 19 04:06:17 PM PDT 24	Mar 19 04:44:00 PM PDT 24	13520242902 ps
T281	/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.2814053238			Mar 19 04:11:43 PM PDT 24	Mar 19 04:41:05 PM PDT 24	9196342010 ps
T282	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1820127748			Mar 19 03:45:16 PM PDT 24	Mar 19 03:49:08 PM PDT 24	3241803772 ps
T218	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2937343376			Mar 19 04:05:58 PM PDT 24	Mar 19 04:14:09 PM PDT 24	3182860724 ps
T919	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.659483549			Mar 19 03:49:05 PM PDT 24	Mar 19 03:57:56 PM PDT 24	3900625640 ps
T784	/workspace/coverage/default/52.chip_sw_all_escalation_resets.2770849473			Mar 19 04:10:49 PM PDT 24	Mar 19 04:24:31 PM PDT 24	5656256832 ps
T193	/workspace/coverage/default/2.rom_e2e_shutdown_output.3558063351			Mar 19 04:09:24 PM PDT 24	Mar 19 04:57:43 PM PDT 24	23256168888 ps
T920	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2514581352			Mar 19 03:51:33 PM PDT 24	Mar 19 04:27:48 PM PDT 24	8357534400 ps
T921	/workspace/coverage/default/2.chip_sw_example_rom.4104515552			Mar 19 03:56:03 PM PDT 24	Mar 19 03:58:18 PM PDT 24	2646454360 ps
T155	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2510599718			Mar 19 04:08:56 PM PDT 24	Mar 19 04:24:35 PM PDT 24	8696302872 ps
T922	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3352260805			Mar 19 03:57:50 PM PDT 24	Mar 19 04:05:06 PM PDT 24	5319445324 ps
T743	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1019278588			Mar 19 04:10:25 PM PDT 24	Mar 19 04:17:51 PM PDT 24	3895904512 ps
T207	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3701938904			Mar 19 04:07:52 PM PDT 24	Mar 19 04:18:53 PM PDT 24	4399309268 ps
T212	/workspace/coverage/default/0.chip_sw_plic_sw_irq.117689332			Mar 19 03:50:31 PM PDT 24	Mar 19 03:54:35 PM PDT 24	2620056350 ps
T238	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2575606408			Mar 19 03:51:06 PM PDT 24	Mar 19 03:57:20 PM PDT 24	3088877601 ps
T19	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1125945785			Mar 19 03:46:48 PM PDT 24	Mar 19 04:07:15 PM PDT 24	22198765334 ps
T239	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2256542492			Mar 19 03:50:18 PM PDT 24	Mar 19 03:54:18 PM PDT 24	2119650528 ps
T240	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1452008200			Mar 19 03:54:30 PM PDT 24	Mar 19 04:04:33 PM PDT 24	4600864369 ps
T241	/workspace/coverage/default/0.chip_sival_flash_info_access.2532141741			Mar 19 03:48:56 PM PDT 24	Mar 19 03:55:27 PM PDT 24	3715221204 ps
T242	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2158219028			Mar 19 03:49:18 PM PDT 24	Mar 19 03:58:08 PM PDT 24	5377640976 ps
T243	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.617012597			Mar 19 03:53:19 PM PDT 24	Mar 19 04:43:51 PM PDT 24	11827772983 ps
T244	/workspace/coverage/default/1.chip_sw_example_manufacturer.4017588828			Mar 19 03:48:01 PM PDT 24	Mar 19 03:51:04 PM PDT 24	2841499678 ps
T923	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1102194089			Mar 19 03:51:35 PM PDT 24	Mar 19 03:56:02 PM PDT 24	3061387807 ps
T258	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.388085645			Mar 19 03:56:05 PM PDT 24	Mar 19 04:07:28 PM PDT 24	5232330752 ps
T116	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2538845318			Mar 19 03:48:39 PM PDT 24	Mar 19 03:50:38 PM PDT 24	2231431983 ps
T924	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3402094498			Mar 19 04:08:19 PM PDT 24	Mar 19 04:12:25 PM PDT 24	2985864015 ps
T925	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2612919198			Mar 19 03:51:49 PM PDT 24	Mar 19 04:00:41 PM PDT 24	4471383632 ps
T926	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4233402089			Mar 19 04:03:17 PM PDT 24	Mar 19 04:07:46 PM PDT 24	2877667757 ps
T927	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3844164316			Mar 19 03:57:18 PM PDT 24	Mar 19 04:09:56 PM PDT 24	9470181182 ps
T928	/workspace/coverage/default/1.chip_sw_csrng_smoketest.1839625352			Mar 19 03:54:14 PM PDT 24	Mar 19 03:58:33 PM PDT 24	2770944272 ps
T929	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3804673887			Mar 19 03:54:56 PM PDT 24	Mar 19 04:24:35 PM PDT 24	6894469369 ps
T156	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4288278596			Mar 19 03:48:07 PM PDT 24	Mar 19 03:56:11 PM PDT 24	5764962424 ps
T339	/workspace/coverage/default/2.chip_sw_all_escalation_resets.343348971			Mar 19 03:55:13 PM PDT 24	Mar 19 04:05:49 PM PDT 24	4576905700 ps
T930	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.734767547			Mar 19 03:47:51 PM PDT 24	Mar 19 03:55:10 PM PDT 24	4774704700 ps
T16	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3913678952			Mar 19 03:51:42 PM PDT 24	Mar 19 03:59:15 PM PDT 24	7004091508 ps