| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| big_delay | 200 | 1 | T502 | 1 | T501 | 1 | T408 | 1 | ||||
| small_delay | 976 | 1 | T66 | 1 | T67 | 1 | T74 | 1 | ||||
| zero | 624 | 1 | T72 | 1 | T73 | 1 | T406 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |