Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	451	1			T404	1		T498	5		T495	4
all_values[1]	460	1			T67	1		T406	1		T404	3
all_values[2]	454	1			T404	1		T720	1		T498	6
all_values[3]	448	1			T67	2		T388	1		T498	8
all_values[4]	459	1			T388	1		T404	3		T498	3
all_values[5]	458	1			T406	1		T404	3		T720	1
all_values[6]	445	1			T67	1		T404	1		T498	2
all_values[7]	423	1			T67	2		T406	1		T388	1
all_values[8]	473	1			T66	1		T67	1		T406	1
all_values[9]	502	1			T67	1		T404	3		T498	1
all_values[10]	431	1			T67	5		T404	2		T498	1
all_values[11]	474	1			T67	2		T498	1		T495	2
all_values[12]	478	1			T406	1		T404	3		T720	2
all_values[13]	448	1			T66	1		T67	2		T406	1
all_values[14]	504	1			T66	1		T406	2		T404	2
all_values[15]	482	1			T67	1		T388	1		T404	5
all_values[16]	446	1			T67	2		T404	2		T498	1
all_values[17]	506	1			T67	2		T404	2		T498	1
all_values[18]	471	1			T67	2		T406	1		T720	2
all_values[19]	493	1			T67	1		T406	2		T404	2
all_values[20]	454	1			T66	1		T67	1		T404	5
all_values[21]	478	1			T67	1		T498	2		T495	4
all_values[22]	504	1			T67	1		T404	2		T720	1
all_values[23]	496	1			T67	3		T406	1		T404	3
all_values[24]	460	1			T66	1		T67	1		T404	3
all_values[25]	460	1			T404	2		T720	1		T495	3
all_values[26]	473	1			T67	3		T406	1		T404	1
all_values[27]	470	1			T67	1		T404	4		T498	4
all_values[28]	468	1			T66	1		T67	1		T404	3
all_values[29]	431	1			T67	1		T404	3		T720	1
all_values[30]	468	1			T67	2		T404	2		T720	1
all_values[31]	454	1			T67	1		T406	2		T404	1
all_values[32]	497	1			T67	3		T406	1		T498	2
all_values[33]	458	1			T67	2		T404	3		T720	2
all_values[34]	451	1			T67	2		T388	2		T404	3
all_values[35]	439	1			T404	2		T498	1		T495	1
all_values[36]	492	1			T67	2		T404	2		T498	3
all_values[37]	452	1			T67	1		T404	3		T498	3
all_values[38]	469	1			T388	1		T404	2		T498	3
all_values[39]	480	1			T67	2		T404	5		T720	1
all_values[40]	462	1			T67	1		T406	2		T388	1
all_values[41]	460	1			T67	1		T404	4		T720	2
all_values[42]	451	1			T67	1		T720	1		T498	1
all_values[43]	431	1			T67	2		T404	1		T720	1
all_values[44]	437	1			T67	2		T404	3		T720	1
all_values[45]	470	1			T66	1		T67	1		T404	3
all_values[46]	476	1			T67	1		T404	1		T498	4
all_values[47]	433	1			T66	1		T67	2		T406	1
all_values[48]	489	1			T67	1		T498	4		T495	1
all_values[49]	473	1			T67	4		T404	3		T498	2