Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3555	1			T67	11		T406	5		T404	17
all_values[1]	3512	1			T67	6		T406	1		T404	28
all_values[2]	3517	1			T67	7		T405	1		T406	1
all_values[3]	3508	1			T67	5		T406	4		T404	17
all_values[4]	3476	1			T67	6		T406	1		T404	24
all_values[5]	3493	1			T67	5		T406	3		T404	17
all_values[6]	3539	1			T67	9		T405	1		T406	2
all_values[7]	3500	1			T67	5		T405	2		T406	1
all_values[8]	3533	1			T67	4		T406	2		T404	24
all_values[9]	3549	1			T67	10		T405	3		T406	3
all_values[10]	3530	1			T67	8		T406	2		T404	30
all_values[11]	3537	1			T67	4		T406	3		T404	24
all_values[12]	3541	1			T67	5		T405	1		T406	4
all_values[13]	3503	1			T67	5		T404	31		T720	1
all_values[14]	3596	1			T67	4		T406	4		T404	20
all_values[15]	3545	1			T67	6		T405	1		T406	1
all_values[16]	3490	1			T67	5		T405	1		T406	1
all_values[17]	3545	1			T67	6		T405	1		T404	26
all_values[18]	3536	1			T67	3		T405	1		T404	24
all_values[19]	3591	1			T67	6		T406	1		T404	18
all_values[20]	3555	1			T67	5		T405	2		T406	1
all_values[21]	3528	1			T67	7		T406	1		T404	27
all_values[22]	3440	1			T67	9		T404	30		T498	10
all_values[23]	3457	1			T67	6		T405	2		T406	1
all_values[24]	3497	1			T67	4		T405	1		T404	24
all_values[25]	3457	1			T67	6		T404	22		T498	17
all_values[26]	3595	1			T67	3		T406	3		T404	16
all_values[27]	3466	1			T67	6		T404	21		T498	13
all_values[28]	3629	1			T67	4		T406	2		T404	25
all_values[29]	3620	1			T67	8		T406	2		T404	23
all_values[30]	3484	1			T67	4		T404	20		T720	2
all_values[31]	3549	1			T67	6		T406	5		T404	19
all_values[32]	3453	1			T67	7		T405	1		T406	3
all_values[33]	3483	1			T67	5		T406	4		T404	25
all_values[34]	3483	1			T67	7		T405	3		T406	5
all_values[35]	3516	1			T67	15		T405	2		T406	3
all_values[36]	3502	1			T67	9		T405	4		T406	2
all_values[37]	3507	1			T67	8		T406	3		T404	26
all_values[38]	3486	1			T67	4		T405	1		T406	1
all_values[39]	3579	1			T67	8		T405	1		T404	30
all_values[40]	3391	1			T67	3		T405	1		T404	29
all_values[41]	3516	1			T67	7		T405	1		T406	3
all_values[42]	3445	1			T67	5		T405	1		T406	2
all_values[43]	3543	1			T67	7		T405	2		T406	4
all_values[44]	3435	1			T67	7		T405	2		T406	2
all_values[45]	3563	1			T67	9		T406	3		T404	23
all_values[46]	3487	1			T67	4		T404	23		T720	3
all_values[47]	3553	1			T67	2		T405	2		T406	1
all_values[48]	3425	1			T67	3		T406	1		T404	18
all_values[49]	3575	1			T67	2		T405	3		T406	2
all_values[50]	3536	1			T67	4		T405	1		T406	3
all_values[51]	3523	1			T67	10		T405	2		T404	25
all_values[52]	3549	1			T67	9		T405	1		T406	3
all_values[53]	3548	1			T67	12		T405	1		T406	1
all_values[54]	3542	1			T67	6		T406	1		T404	24
all_values[55]	3540	1			T67	8		T406	3		T404	24
all_values[56]	3621	1			T67	7		T405	1		T406	1
all_values[57]	3443	1			T67	5		T405	2		T406	2
all_values[58]	3448	1			T67	12		T405	2		T406	4
all_values[59]	3569	1			T67	12		T406	4		T404	24
all_values[60]	3490	1			T67	7		T406	7		T404	31
all_values[61]	3540	1			T67	3		T405	1		T406	1
all_values[62]	3494	1			T67	5		T405	3		T406	5
all_values[63]	3514	1			T67	4		T404	20		T720	1