Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	544	1			T401	1		T485	1		T487	1
all_values[1]	471	1			T400	1		T485	2		T491	1
all_values[2]	472	1			T401	1		T487	2		T491	3
all_values[3]	488	1			T400	1		T485	2		T491	6
all_values[4]	484	1			T400	3		T485	2		T491	4
all_values[5]	499	1			T400	2		T401	1		T487	1
all_values[6]	462	1			T400	1		T401	1		T485	1
all_values[7]	535	1			T400	3		T485	1		T491	3
all_values[8]	524	1			T400	3		T485	1		T491	2
all_values[9]	514	1			T401	1		T485	4		T491	2
all_values[10]	550	1			T400	1		T401	1		T485	1
all_values[11]	525	1			T400	1		T485	4		T491	4
all_values[12]	527	1			T400	1		T485	1		T491	4
all_values[13]	506	1			T400	1		T401	3		T485	2
all_values[14]	488	1			T400	1		T401	2		T485	3
all_values[15]	490	1			T400	4		T401	1		T485	5
all_values[16]	498	1			T485	5		T491	3		T378	1
all_values[17]	503	1			T400	1		T401	2		T485	2
all_values[18]	497	1			T400	3		T487	1		T491	4
all_values[19]	492	1			T401	3		T485	1		T491	1
all_values[20]	507	1			T400	1		T485	3		T491	3
all_values[21]	488	1			T400	2		T485	6		T491	3
all_values[22]	479	1			T400	4		T485	2		T491	4
all_values[23]	502	1			T401	1		T485	1		T491	3
all_values[24]	519	1			T400	1		T401	1		T485	3
all_values[25]	507	1			T400	2		T485	1		T491	1
all_values[26]	482	1			T400	2		T485	3		T487	1
all_values[27]	467	1			T400	1		T485	4		T491	2
all_values[28]	543	1			T485	1		T491	8		T490	1
all_values[29]	452	1			T401	1		T485	1		T487	1
all_values[30]	494	1			T400	3		T485	2		T491	7
all_values[31]	505	1			T400	3		T485	3		T491	2
all_values[32]	540	1			T400	1		T485	4		T491	2
all_values[33]	513	1			T401	1		T485	2		T487	1
all_values[34]	501	1			T400	4		T401	2		T485	5
all_values[35]	521	1			T401	1		T485	2		T491	3
all_values[36]	498	1			T400	2		T485	2		T491	2
all_values[37]	487	1			T485	3		T487	1		T491	2
all_values[38]	501	1			T400	1		T491	3		T490	1
all_values[39]	497	1			T400	2		T401	1		T485	2
all_values[40]	511	1			T400	2		T491	2		T738	1
all_values[41]	455	1			T400	2		T485	1		T491	4
all_values[42]	483	1			T401	1		T485	6		T491	2
all_values[43]	483	1			T400	1		T485	1		T487	1
all_values[44]	528	1			T400	2		T401	1		T485	3
all_values[45]	490	1			T400	1		T485	3		T491	6
all_values[46]	496	1			T400	1		T401	1		T485	1
all_values[47]	536	1			T400	1		T401	1		T485	1
all_values[48]	492	1			T400	2		T485	4		T491	7
all_values[49]	542	1			T401	1		T491	3		T738	1