Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.47	94.22	95.06		94.93	97.38	99.53

Total tests in report: 2823

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.48	40.48	45.58	45.58	43.17	43.17	32.27	32.27			58.28	58.28	63.22	63.22	0.39	0.39	/workspace/coverage/default/36.chip_sw_all_escalation_resets.799356090
50.35	9.87	54.11	8.53	52.70	9.53	36.60	4.34			66.85	8.56	91.13	27.91	0.74	0.35	/workspace/coverage/default/1.chip_jtag_csr_rw.3724021599
55.65	5.30	65.70	11.59	60.05	7.34	39.44	2.84			76.87	10.03	91.13	0.00	0.74	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.741372485
60.39	4.73	75.68	9.98	62.34	2.29	45.84	6.40			77.21	0.34	91.13	0.00	10.13	9.39	/workspace/coverage/cover_reg_top/3.xbar_stress_all.2982434431
64.61	4.23	75.71	0.04	64.29	1.96	45.84	0.00			77.29	0.08	91.13	0.00	33.40	23.28	/workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.937014578
67.55	2.94	79.02	3.30	72.00	7.71	46.51	0.67			82.13	4.84	91.13	0.00	34.51	1.10	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.4292075971
70.32	2.77	79.02	0.00	72.29	0.28	46.51	0.00			82.15	0.02	91.13	0.00	50.83	16.32	/workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.967266233
73.06	2.75	79.02	0.01	72.31	0.02	62.94	16.43			82.16	0.02	91.13	0.00	50.83	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.875236660
75.39	2.33	84.25	5.22	76.10	3.79	66.37	3.44			83.68	1.52	91.13	0.00	50.83	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.237841119
77.30	1.91	85.40	1.15	78.49	2.39	70.62	4.25			85.37	1.69	91.31	0.18	52.61	1.79	/workspace/coverage/default/2.chip_sw_alert_test.4206330945
79.20	1.90	85.40	0.00	78.74	0.25	70.62	0.00			85.42	0.05	91.31	0.00	63.73	11.12	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3845996973
80.70	1.50	85.40	0.00	78.82	0.08	70.62	0.00			85.42	0.00	91.31	0.00	72.64	8.91	/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3407026385
81.97	1.27	87.48	2.08	80.85	2.03	71.73	1.11			87.84	2.42	91.31	0.00	72.64	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1036587746
83.12	1.15	87.48	0.00	80.91	0.06	71.73	0.00			87.84	0.00	91.31	0.00	79.47	6.84	/workspace/coverage/cover_reg_top/48.xbar_access_same_device.1594198023
84.14	1.01	87.48	0.00	80.91	0.00	77.82	6.09			87.84	0.00	91.31	0.00	79.47	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.369204135
85.09	0.95	88.70	1.22	82.89	1.98	78.19	0.37			89.78	1.94	91.50	0.18	79.47	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.137451838
85.93	0.84	88.70	0.00	83.32	0.43	78.19	0.00			89.87	0.10	91.50	0.00	83.99	4.51	/workspace/coverage/cover_reg_top/42.xbar_stress_all.182409771
86.76	0.84	90.14	1.45	83.96	0.64	80.55	2.36			90.26	0.39	91.68	0.18	83.99	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4246388230
87.53	0.77	90.43	0.29	84.08	0.12	80.58	0.03			90.38	0.12	95.75	4.07	83.99	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2077564720
88.18	0.65	91.46	1.02	84.92	0.84	81.12	0.54			91.30	0.92	96.30	0.55	83.99	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2740963138
88.82	0.64	91.49	0.04	85.15	0.22	81.88	0.75			91.34	0.04	96.30	0.00	86.77	2.78	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.569942003
89.41	0.59	91.50	0.01	85.15	0.01	85.40	3.52			91.34	0.00	96.30	0.00	86.77	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.806134678
89.98	0.57	92.44	0.93	86.25	1.10	85.84	0.44			92.31	0.97	96.30	0.00	86.77	0.00	/workspace/coverage/default/0.chip_sw_gpio_smoketest.598749584
90.55	0.57	92.45	0.01	89.25	3.00	85.84	0.00			92.31	0.00	96.30	0.00	87.16	0.39	/workspace/coverage/cover_reg_top/12.chip_tl_errors.1163153343
91.12	0.56	92.45	0.00	89.25	0.00	85.84	0.00			92.31	0.00	96.30	0.00	90.54	3.38	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2498499667
91.51	0.39	92.45	0.00	89.36	0.10	85.84	0.00			92.33	0.02	96.30	0.00	92.77	2.23	/workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3584398377
91.86	0.35	92.45	0.00	89.36	0.01	85.84	0.00			92.33	0.00	96.30	0.00	94.89	2.11	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2292955112
92.19	0.33	92.54	0.09	89.37	0.01	87.69	1.85			92.34	0.01	96.30	0.00	94.90	0.01	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2136261025
92.51	0.32	93.07	0.54	89.87	0.50	88.06	0.37			92.83	0.49	96.30	0.00	94.90	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2141271214
92.79	0.29	93.13	0.06	89.90	0.03	89.66	1.60			92.86	0.02	96.30	0.00	94.90	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2594496520
93.00	0.21	93.13	0.00	89.94	0.04	89.66	0.00			92.86	0.00	96.30	0.00	96.11	1.21	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3827566773
93.16	0.17	93.36	0.23	90.17	0.23	89.90	0.25			93.14	0.29	96.30	0.00	96.11	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.857526968
93.31	0.15	93.58	0.22	90.49	0.33	90.26	0.36			93.14	0.00	96.30	0.00	96.11	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1166208117
93.46	0.14	93.83	0.26	90.61	0.12	90.66	0.40			93.21	0.07	96.30	0.00	96.12	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2020931221
93.60	0.14	93.87	0.04	90.96	0.35	90.71	0.05			93.61	0.40	96.30	0.00	96.12	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1499326395
93.73	0.13	93.87	0.00	90.96	0.00	90.71	0.00			93.61	0.00	96.30	0.00	96.90	0.78	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1926145643
93.85	0.12	94.12	0.24	91.18	0.21	90.71	0.00			93.87	0.26	96.30	0.00	96.90	0.00	/workspace/coverage/cover_reg_top/13.chip_csr_rw.1004896953
93.96	0.12	94.12	0.00	91.18	0.00	90.71	0.00			93.87	0.00	96.30	0.00	97.59	0.69	/workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.1678045683
94.07	0.11	94.12	0.00	91.18	0.00	91.37	0.66			93.87	0.00	96.30	0.00	97.59	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1771156566
94.17	0.10	94.12	0.00	91.38	0.21	91.37	0.00			93.90	0.03	96.30	0.00	97.97	0.38	/workspace/coverage/cover_reg_top/7.xbar_stress_all.2965784578
94.27	0.09	94.30	0.18	91.45	0.06	91.47	0.09			93.94	0.04	96.49	0.18	97.97	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3641335592
94.36	0.09	94.30	0.01	91.47	0.02	91.97	0.51			93.95	0.01	96.49	0.00	97.97	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3826693757
94.44	0.08	94.38	0.08	91.65	0.18	92.10	0.12			94.05	0.10	96.49	0.00	97.97	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1890549905
94.52	0.08	94.38	0.00	91.65	0.00	92.58	0.49			94.05	0.00	96.49	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1431522960
94.60	0.08	94.39	0.01	91.86	0.21	92.60	0.01			94.28	0.23	96.49	0.00	97.97	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3539884012
94.67	0.07	94.39	0.00	91.86	0.00	93.03	0.44			94.28	0.00	96.49	0.00	97.97	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2085412971
94.74	0.07	94.39	0.00	92.25	0.39	93.03	0.00			94.28	0.00	96.49	0.00	98.00	0.04	/workspace/coverage/cover_reg_top/25.chip_tl_errors.1245668096
94.80	0.05	94.51	0.11	92.34	0.09	93.07	0.03			94.38	0.10	96.49	0.00	98.00	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2113601357
94.85	0.05	94.58	0.08	92.34	0.00	93.31	0.24			94.39	0.01	96.49	0.00	98.00	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.208368785
94.90	0.05	94.65	0.07	92.49	0.15	93.31	0.00			94.47	0.08	96.49	0.00	98.00	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1669503188
94.95	0.05	94.69	0.04	92.58	0.09	93.37	0.07			94.57	0.10	96.49	0.00	98.00	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2781237770
95.00	0.05	94.69	0.00	92.58	0.00	93.67	0.29			94.57	0.00	96.49	0.00	98.00	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.731009630
95.04	0.04	94.70	0.01	92.60	0.01	93.67	0.00			94.60	0.02	96.67	0.18	98.01	0.01	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2274149896
95.08	0.04	94.73	0.03	92.60	0.01	93.67	0.01			94.60	0.01	96.86	0.18	98.03	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3258044165
95.12	0.04	94.73	0.01	92.62	0.01	93.68	0.01			94.61	0.01	97.04	0.18	98.04	0.01	/workspace/coverage/default/85.chip_sw_all_escalation_resets.3951608946
95.16	0.04	94.74	0.01	92.63	0.01	93.68	0.00			94.62	0.01	97.23	0.18	98.05	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.930780382
95.19	0.03	94.74	0.00	92.84	0.21	93.68	0.00			94.62	0.00	97.23	0.00	98.05	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3965581193
95.23	0.03	94.74	0.00	92.85	0.01	93.68	0.00			94.62	0.00	97.23	0.00	98.24	0.19	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.680665426
95.26	0.03	94.74	0.00	92.85	0.00	93.68	0.00			94.62	0.00	97.41	0.18	98.24	0.00	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.327262653
95.29	0.03	94.74	0.00	92.85	0.00	93.86	0.18			94.62	0.00	97.41	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1862560578
95.32	0.03	94.74	0.00	92.85	0.00	94.03	0.18			94.62	0.00	97.41	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4012370681
95.34	0.03	94.76	0.02	92.88	0.04	94.11	0.07			94.66	0.04	97.41	0.00	98.24	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1062466118
95.37	0.03	94.76	0.00	93.05	0.16	94.11	0.00			94.66	0.00	97.41	0.00	98.24	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.3246092471
95.40	0.03	94.83	0.07	93.07	0.03	94.12	0.01			94.71	0.05	97.41	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.410631255
95.42	0.03	94.83	0.00	93.07	0.00	94.28	0.16			94.71	0.00	97.41	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1637114624
95.45	0.03	94.90	0.07	93.12	0.05	94.28	0.00			94.74	0.03	97.41	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1092404239
95.47	0.02	94.90	0.00	93.18	0.05	94.28	0.00			94.76	0.02	97.41	0.00	98.30	0.06	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2810569409
95.49	0.02	94.95	0.05	93.22	0.05	94.28	0.00			94.78	0.02	97.41	0.00	98.30	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2768877233
95.51	0.02	94.95	0.00	93.22	0.00	94.40	0.12			94.78	0.00	97.41	0.00	98.30	0.00	/workspace/coverage/default/0.chip_sw_flash_init.1841074580
95.53	0.02	94.95	0.00	93.26	0.04	94.40	0.00			94.79	0.02	97.41	0.00	98.36	0.06	/workspace/coverage/cover_reg_top/15.xbar_stress_all.1103901556
95.55	0.02	94.98	0.03	93.31	0.05	94.41	0.01			94.82	0.02	97.41	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2370608682
95.56	0.02	95.00	0.02	93.36	0.05	94.43	0.02			94.83	0.02	97.41	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3055880847
95.58	0.02	95.00	0.00	93.36	0.00	94.43	0.00			94.83	0.00	97.41	0.00	98.45	0.09	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1394372496
95.59	0.02	95.00	0.00	93.36	0.00	94.52	0.09			94.83	0.00	97.41	0.00	98.45	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3251253438
95.61	0.02	95.02	0.02	93.40	0.04	94.54	0.03			94.83	0.00	97.41	0.00	98.45	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2971795346
95.62	0.01	95.02	0.00	93.47	0.08	94.54	0.00			94.83	0.00	97.41	0.00	98.46	0.01	/workspace/coverage/cover_reg_top/21.chip_tl_errors.1004474618
95.64	0.01	95.03	0.01	93.52	0.04	94.55	0.01			94.86	0.02	97.41	0.00	98.46	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3931155642
95.65	0.01	95.03	0.00	93.52	0.00	94.55	0.00			94.86	0.00	97.41	0.00	98.54	0.08	/workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3496608468
95.67	0.01	95.03	0.00	93.60	0.08	94.55	0.00			94.86	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.621233992
95.68	0.01	95.03	0.00	93.60	0.00	94.62	0.07			94.86	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/default/74.chip_sw_all_escalation_resets.4004537907
95.69	0.01	95.03	0.00	93.60	0.01	94.62	0.00			94.86	0.00	97.41	0.00	98.60	0.06	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1271919171
95.70	0.01	95.03	0.00	93.66	0.05	94.62	0.00			94.86	0.00	97.41	0.00	98.61	0.01	/workspace/coverage/cover_reg_top/13.chip_tl_errors.2311474232
95.71	0.01	95.06	0.04	93.68	0.02	94.62	0.00			94.87	0.01	97.41	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1891753165
95.72	0.01	95.06	0.00	93.69	0.01	94.62	0.00			94.87	0.00	97.41	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.191220041
95.73	0.01	95.09	0.02	93.69	0.01	94.63	0.01			94.88	0.02	97.41	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3095273528
95.74	0.01	95.09	0.00	93.69	0.00	94.68	0.05			94.88	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1343033572
95.74	0.01	95.11	0.02	93.70	0.01	94.68	0.01			94.90	0.02	97.41	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3787826792
95.75	0.01	95.11	0.00	93.70	0.00	94.73	0.05			94.90	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1079508126
95.76	0.01	95.11	0.00	93.75	0.05	94.73	0.00			94.90	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/61.xbar_stress_all.433558620
95.77	0.01	95.11	0.00	93.79	0.05	94.73	0.00			94.90	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3054567339
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95.93	0.01	95.14	0.00	94.10	0.00	94.95	0.00			94.92	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134184866
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96.01	0.01	95.14	0.00	94.10	0.00	94.95	0.00			94.92	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/89.chip_sw_all_escalation_resets.3957203453
96.01	0.01	95.14	0.00	94.10	0.00	94.95	0.00			94.92	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.461483697
96.01	0.01	95.14	0.00	94.12	0.01	94.95	0.00			94.92	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.344410758
96.01	0.01	95.14	0.01	94.12	0.01	94.95	0.00			94.92	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2705033608
96.01	0.01	95.15	0.01	94.12	0.00	94.96	0.01			94.92	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1647948710
96.02	0.01	95.15	0.00	94.12	0.00	94.96	0.01			94.92	0.01	97.41	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2770930254
96.02	0.01	95.15	0.01	94.12	0.00	94.96	0.01			94.92	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.344994967
96.02	0.01	95.15	0.00	94.12	0.00	94.97	0.01			94.92	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.691642599
96.02	0.01	95.15	0.00	94.12	0.00	94.98	0.01			94.92	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3502979446
96.02	0.01	95.15	0.00	94.12	0.00	94.99	0.01			94.92	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.2759317533
96.02	0.01	95.15	0.00	94.12	0.01	94.99	0.01			94.92	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_hmac_enc.1216185061
96.02	0.01	95.15	0.00	94.12	0.00	94.99	0.00			94.93	0.01	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_tap_straps_dev.1036814659
96.03	0.01	95.15	0.00	94.13	0.01	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.3206505044
96.03	0.01	95.15	0.00	94.14	0.01	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/19.xbar_same_source.4074070133
96.03	0.01	95.15	0.00	94.14	0.01	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.990921160
96.03	0.01	95.15	0.00	94.15	0.01	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all.1740304567
96.03	0.01	95.15	0.00	94.16	0.01	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3631808206
96.03	0.01	95.15	0.00	94.17	0.01	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.521914998
96.03	0.01	95.15	0.00	94.17	0.01	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_gpio.2630072694
96.03	0.01	95.16	0.01	94.18	0.01	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/6.chip_csr_rw.2573883238
96.04	0.01	95.16	0.01	94.18	0.00	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3450795455
96.04	0.01	95.17	0.01	94.18	0.00	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1227272377
96.04	0.01	95.18	0.01	94.18	0.00	94.99	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.4262480835
96.04	0.01	95.18	0.00	94.18	0.00	95.00	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3946706518
96.04	0.01	95.18	0.00	94.18	0.00	95.01	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.187413294
96.04	0.01	95.18	0.00	94.18	0.00	95.01	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1973005296
96.04	0.01	95.18	0.00	94.18	0.00	95.02	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3116956301
96.04	0.01	95.18	0.00	94.18	0.00	95.02	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2970924697
96.04	0.01	95.18	0.00	94.18	0.00	95.03	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2316948176
96.04	0.01	95.18	0.00	94.18	0.00	95.03	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1352572483
96.04	0.01	95.18	0.00	94.18	0.00	95.04	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3198724373
96.05	0.01	95.18	0.00	94.18	0.00	95.04	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1543072335
96.05	0.01	95.18	0.00	94.18	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2080329251
96.05	0.01	95.18	0.00	94.18	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1931976007
96.05	0.01	95.18	0.00	94.19	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/17.xbar_stress_all.3770996714
96.05	0.01	95.18	0.00	94.19	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/22.xbar_error_random.337000340
96.05	0.01	95.18	0.00	94.19	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.180950307
96.05	0.01	95.18	0.00	94.20	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.302550851
96.05	0.01	95.18	0.00	94.20	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3989520934
96.05	0.01	95.18	0.00	94.21	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.4050777569
96.05	0.01	95.18	0.00	94.21	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2785287689
96.05	0.01	95.18	0.00	94.21	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2380295085
96.05	0.01	95.18	0.00	94.22	0.01	95.04	0.00			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3500892113
96.05	0.01	95.18	0.00	94.22	0.00	95.05	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.1533327273
96.05	0.01	95.18	0.00	94.22	0.00	95.05	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.568776222
96.05	0.01	95.18	0.00	94.22	0.00	95.05	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2098039752
96.05	0.01	95.18	0.00	94.22	0.00	95.05	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2507667336
96.05	0.01	95.18	0.00	94.22	0.00	95.06	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1766593451
96.05	0.01	95.18	0.00	94.22	0.00	95.06	0.01			94.93	0.00	97.41	0.00	99.53	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2187984940

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2154774064
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1282484734
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2245441858
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3626310952
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3940674069
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2211791694
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2739349609
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2174836871
/workspace/coverage/cover_reg_top/0.xbar_error_random.94493491
/workspace/coverage/cover_reg_top/0.xbar_random.3425044788
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3340509336
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2132228254
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1667235269
/workspace/coverage/cover_reg_top/0.xbar_same_source.4172572407
/workspace/coverage/cover_reg_top/0.xbar_smoke.822496563
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1602209269
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2768014134
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.4179627797
/workspace/coverage/cover_reg_top/0.xbar_stress_all.119842317
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.894373040
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1950019465
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3651788302
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1961427888
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1024113393
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3432953090
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3003369319
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2571135262
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3453754305
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1165835431
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1056105988
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2488287421
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1771322837
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1582601067
/workspace/coverage/cover_reg_top/1.xbar_error_random.3241158851
/workspace/coverage/cover_reg_top/1.xbar_random.3662646128
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3631496595
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2379049397
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1222612651
/workspace/coverage/cover_reg_top/1.xbar_same_source.1709861687
/workspace/coverage/cover_reg_top/1.xbar_smoke.814280070
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2881700136
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2134447052
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2683526678
/workspace/coverage/cover_reg_top/1.xbar_stress_all.4018684831
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.650473692
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1869344032
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3255496227
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3126213799
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3516072419
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.425875582
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1827494735
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2327063919
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2146197446
/workspace/coverage/cover_reg_top/10.xbar_error_random.3231310092
/workspace/coverage/cover_reg_top/10.xbar_random.2850037541
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3867007634
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2334730457
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1921455643
/workspace/coverage/cover_reg_top/10.xbar_same_source.269426441
/workspace/coverage/cover_reg_top/10.xbar_smoke.2158058481
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2786645120
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2185820384
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2688903743
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3675072554
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2203797527
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1511907699
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1214835477
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1732700553
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.126133390
/workspace/coverage/cover_reg_top/11.chip_tl_errors.641813873
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2681463460
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3013154902
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3266088670
/workspace/coverage/cover_reg_top/11.xbar_error_random.1779142544
/workspace/coverage/cover_reg_top/11.xbar_random.1501753906
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1436229020
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3108368641
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.747560205
/workspace/coverage/cover_reg_top/11.xbar_same_source.544910364
/workspace/coverage/cover_reg_top/11.xbar_smoke.2536543690
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.280782002
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1079747886
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2875430968
/workspace/coverage/cover_reg_top/11.xbar_stress_all.656197314
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2040744757
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3050245534
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1978782043
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1965047965
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3970136369
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.478839826
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1446098090
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.371427636
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2951280621
/workspace/coverage/cover_reg_top/12.xbar_error_random.2638083132
/workspace/coverage/cover_reg_top/12.xbar_random.3194657634
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3473683613
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3003986527
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1260844542
/workspace/coverage/cover_reg_top/12.xbar_same_source.3242658836
/workspace/coverage/cover_reg_top/12.xbar_smoke.2135868709
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3724685594
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2929397685
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1350740349
/workspace/coverage/cover_reg_top/12.xbar_stress_all.4293650492
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3620426843
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.155795970
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.738758396
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2653423457
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.177461055
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1851543218
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1110198218
/workspace/coverage/cover_reg_top/13.xbar_error_random.2444962626
/workspace/coverage/cover_reg_top/13.xbar_random.4131344203
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.447659305
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1740570225
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3620294619
/workspace/coverage/cover_reg_top/13.xbar_same_source.954341588
/workspace/coverage/cover_reg_top/13.xbar_smoke.2225783170
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2394301301
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1985328947
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2700846017
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2410078111
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.509393155
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2792581758
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/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1882497680
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1560266021
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2126601365
/workspace/coverage/default/39.chip_sw_all_escalation_resets.649378310
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3127856947
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2313037194
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3273015455
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3568840312
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2272274998
/workspace/coverage/default/4.chip_sw_uart_tx_rx.325941090
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1927115189
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.268285259
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.4166392533
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.125417519
/workspace/coverage/default/4.chip_tap_straps_dev.1612104812
/workspace/coverage/default/4.chip_tap_straps_prod.2862874614
/workspace/coverage/default/4.chip_tap_straps_rma.732030318
/workspace/coverage/default/4.chip_tap_straps_testunlock0.674450877
/workspace/coverage/default/40.chip_sw_all_escalation_resets.4012077371
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1828303731
/workspace/coverage/default/41.chip_sw_all_escalation_resets.4223488557
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2946091202
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1655461986
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2239969090
/workspace/coverage/default/47.chip_sw_all_escalation_resets.643578675
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.583640886
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1047563295
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1754371790
/workspace/coverage/default/5.chip_sw_all_escalation_resets.191654927
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3729778358
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.717319281
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2253819759
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1070207362
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1431583394
/workspace/coverage/default/52.chip_sw_all_escalation_resets.642242330
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503601002
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1187959745
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1375472907
/workspace/coverage/default/56.chip_sw_all_escalation_resets.899021882
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1851629659
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3612622787
/workspace/coverage/default/58.chip_sw_all_escalation_resets.4188171636
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4274120548
/workspace/coverage/default/59.chip_sw_all_escalation_resets.758379072
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2861549124
/workspace/coverage/default/6.chip_sw_all_escalation_resets.4281456381
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.162572429
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3445430722
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2418299471
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.13670511
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3840982091
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1013567904
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853038374
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1580598937
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.741115708
/workspace/coverage/default/64.chip_sw_all_escalation_resets.442762722
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3220292667
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2567622884
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3707209656
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3200238645
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630359308
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2873718630
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2308840127
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3540358038
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.75704829
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2301601028
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2070247000
/workspace/coverage/default/70.chip_sw_all_escalation_resets.748638212
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3137419675
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3726955323
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2952909077
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1021875095
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1745534951
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.883679099
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1045926724
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2419097503
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3217762660
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.4035951735
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2180040583
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3241398404
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3815148626
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3615710568
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3218777662
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2505105516
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.942174376
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1692625927
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.493439998
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2228460352
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3319199341
/workspace/coverage/default/82.chip_sw_all_escalation_resets.280251320
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1936578896
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1075594615
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.883789008
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2108492786
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1070305377
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1187092362
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2698629128
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3092675166
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3099720164
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3669737212
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.411437755
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.513333039
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3894090083
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1065506931
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1485017805
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3417205506
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2086704596
/workspace/coverage/default/93.chip_sw_all_escalation_resets.741427237
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3840068639
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1944487375
/workspace/coverage/default/97.chip_sw_all_escalation_resets.76531657
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3894048675
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3422189429
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.256795404
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3510154588
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2867983573
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1371720437
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.773198937
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1605794242
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1896847140
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3484118817

---

Total test records in report: 2823

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.chip_sw_example_flash.3551008786			Mar 21 03:59:34 PM PDT 24	Mar 21 04:03:10 PM PDT 24	2473732000 ps
T2	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1862560578			Mar 21 04:03:29 PM PDT 24	Mar 21 04:07:36 PM PDT 24	2426945760 ps
T3	/workspace/coverage/default/94.chip_sw_all_escalation_resets.1003366342			Mar 21 04:33:10 PM PDT 24	Mar 21 04:41:05 PM PDT 24	5740380310 ps
T32	/workspace/coverage/default/36.chip_sw_all_escalation_resets.799356090			Mar 21 04:27:24 PM PDT 24	Mar 21 04:37:04 PM PDT 24	5087057870 ps
T82	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1070894718			Mar 21 04:12:03 PM PDT 24	Mar 21 04:18:21 PM PDT 24	3466739369 ps
T33	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2594496520			Mar 21 04:14:07 PM PDT 24	Mar 21 04:31:32 PM PDT 24	6685929216 ps
T83	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.133631612			Mar 21 04:22:13 PM PDT 24	Mar 21 04:28:30 PM PDT 24	3307294602 ps
T84	/workspace/coverage/default/1.chip_sw_example_flash.2476157343			Mar 21 04:03:33 PM PDT 24	Mar 21 04:06:58 PM PDT 24	3025375874 ps
T85	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2601695429			Mar 21 04:16:08 PM PDT 24	Mar 21 04:40:42 PM PDT 24	6310576332 ps
T64	/workspace/coverage/default/74.chip_sw_all_escalation_resets.4004537907			Mar 21 04:30:29 PM PDT 24	Mar 21 04:40:01 PM PDT 24	5487756968 ps
T60	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2020931221			Mar 21 04:25:57 PM PDT 24	Mar 21 04:33:57 PM PDT 24	3799187610 ps
T61	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1269806743			Mar 21 04:26:57 PM PDT 24	Mar 21 04:33:51 PM PDT 24	3636346076 ps
T145	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3933986387			Mar 21 04:12:49 PM PDT 24	Mar 21 04:21:34 PM PDT 24	4420719470 ps
T62	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4274120548			Mar 21 04:29:01 PM PDT 24	Mar 21 04:35:07 PM PDT 24	3643373080 ps
T44	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2770930254			Mar 21 04:19:27 PM PDT 24	Mar 21 04:27:25 PM PDT 24	5710580726 ps
T150	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.496821935			Mar 21 04:12:40 PM PDT 24	Mar 21 04:33:50 PM PDT 24	9707450920 ps
T162	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.4238646626			Mar 21 04:07:44 PM PDT 24	Mar 21 04:11:49 PM PDT 24	2375995760 ps
T113	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.875236660			Mar 21 04:00:08 PM PDT 24	Mar 21 04:06:30 PM PDT 24	4390068068 ps
T163	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1355344273			Mar 21 03:57:48 PM PDT 24	Mar 21 04:16:44 PM PDT 24	6006204724 ps
T10	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1890549905			Mar 21 04:14:48 PM PDT 24	Mar 21 04:27:31 PM PDT 24	6202226235 ps
T45	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.540888798			Mar 21 03:58:16 PM PDT 24	Mar 21 04:02:46 PM PDT 24	3387641982 ps
T392	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1979816641			Mar 21 04:13:44 PM PDT 24	Mar 21 04:31:43 PM PDT 24	5627985096 ps
T46	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2773380660			Mar 21 04:10:10 PM PDT 24	Mar 21 04:17:34 PM PDT 24	4478144854 ps
T184	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.805437250			Mar 21 03:58:03 PM PDT 24	Mar 21 04:06:07 PM PDT 24	3679750250 ps
T329	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2419097503			Mar 21 04:28:25 PM PDT 24	Mar 21 04:33:41 PM PDT 24	4261899460 ps
T330	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.758946675			Mar 21 04:27:12 PM PDT 24	Mar 21 04:33:17 PM PDT 24	3453591688 ps
T4	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2136261025			Mar 21 04:05:09 PM PDT 24	Mar 21 06:55:41 PM PDT 24	57658957393 ps
T70	/workspace/coverage/default/3.chip_tap_straps_dev.3196287631			Mar 21 04:22:35 PM PDT 24	Mar 21 04:35:46 PM PDT 24	7986928268 ps
T155	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3931155642			Mar 21 04:10:25 PM PDT 24	Mar 21 04:20:54 PM PDT 24	5225821388 ps
T379	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.841907962			Mar 21 04:05:14 PM PDT 24	Mar 21 04:10:21 PM PDT 24	3449287912 ps
T185	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3822281503			Mar 21 04:29:15 PM PDT 24	Mar 21 04:38:39 PM PDT 24	5855372684 ps
T42	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4246388230			Mar 21 04:04:24 PM PDT 24	Mar 21 04:40:26 PM PDT 24	8749507008 ps
T120	/workspace/coverage/default/1.chip_sw_power_sleep_load.2758791374			Mar 21 04:11:07 PM PDT 24	Mar 21 04:19:12 PM PDT 24	9908585828 ps
T133	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1343033572			Mar 21 03:59:08 PM PDT 24	Mar 21 04:07:24 PM PDT 24	3987275144 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2910011092			Mar 21 03:57:26 PM PDT 24	Mar 21 04:01:53 PM PDT 24	3299182452 ps
T164	/workspace/coverage/default/2.chip_sw_otbn_randomness.3284397684			Mar 21 04:20:28 PM PDT 24	Mar 21 04:35:48 PM PDT 24	6262301800 ps
T57	/workspace/coverage/default/2.chip_sw_alert_test.4206330945			Mar 21 04:15:27 PM PDT 24	Mar 21 04:20:27 PM PDT 24	2755773874 ps
T206	/workspace/coverage/default/29.chip_sw_all_escalation_resets.4180422623			Mar 21 04:26:46 PM PDT 24	Mar 21 04:36:42 PM PDT 24	6355795840 ps
T264	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1442250604			Mar 21 03:58:57 PM PDT 24	Mar 21 04:04:04 PM PDT 24	2996888924 ps
T5	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2273819836			Mar 21 04:05:16 PM PDT 24	Mar 21 04:45:51 PM PDT 24	8646758900 ps
T159	/workspace/coverage/default/1.chip_sw_edn_auto_mode.806134678			Mar 21 04:05:22 PM PDT 24	Mar 21 04:39:09 PM PDT 24	7279718090 ps
T265	/workspace/coverage/default/0.chip_plic_all_irqs_20.741372485			Mar 21 04:00:35 PM PDT 24	Mar 21 04:16:27 PM PDT 24	5026315672 ps
T266	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1271047814			Mar 21 04:02:53 PM PDT 24	Mar 21 04:13:18 PM PDT 24	3875025644 ps
T192	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.316015758			Mar 21 04:23:22 PM PDT 24	Mar 21 04:32:24 PM PDT 24	4608257375 ps
T108	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4234570231			Mar 21 03:58:55 PM PDT 24	Mar 21 05:00:09 PM PDT 24	18735451138 ps
T68	/workspace/coverage/default/3.chip_tap_straps_prod.2985948443			Mar 21 04:20:48 PM PDT 24	Mar 21 04:23:21 PM PDT 24	2984512378 ps
T599	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2418847208			Mar 21 04:03:56 PM PDT 24	Mar 21 04:14:01 PM PDT 24	5429533740 ps
T394	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.648629223			Mar 21 03:59:37 PM PDT 24	Mar 21 04:20:56 PM PDT 24	6794428739 ps
T231	/workspace/coverage/default/0.chip_sw_plic_sw_irq.344994967			Mar 21 03:59:48 PM PDT 24	Mar 21 04:05:11 PM PDT 24	3079389760 ps
T633	/workspace/coverage/default/0.chip_sw_aes_entropy.1368155142			Mar 21 04:00:04 PM PDT 24	Mar 21 04:04:19 PM PDT 24	2080041508 ps
T43	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2972475486			Mar 21 04:05:54 PM PDT 24	Mar 21 04:40:18 PM PDT 24	8469562128 ps
T118	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2781237770			Mar 21 03:57:28 PM PDT 24	Mar 21 04:28:39 PM PDT 24	13712725050 ps
T109	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4012370681			Mar 21 04:05:57 PM PDT 24	Mar 21 04:25:51 PM PDT 24	5576307640 ps
T298	/workspace/coverage/default/1.chip_sw_otbn_randomness.3442977929			Mar 21 04:04:59 PM PDT 24	Mar 21 04:20:17 PM PDT 24	5572305960 ps
T609	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.741115708			Mar 21 04:27:35 PM PDT 24	Mar 21 04:34:29 PM PDT 24	3844440384 ps
T323	/workspace/coverage/default/1.chip_sw_aon_timer_irq.2152106546			Mar 21 04:04:27 PM PDT 24	Mar 21 04:12:02 PM PDT 24	3917999846 ps
T132	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3251253438			Mar 21 04:19:04 PM PDT 24	Mar 21 04:28:30 PM PDT 24	3343580958 ps
T121	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3280269695			Mar 21 04:23:27 PM PDT 24	Mar 21 04:31:16 PM PDT 24	7447995874 ps
T196	/workspace/coverage/default/4.chip_sw_uart_tx_rx.325941090			Mar 21 04:22:44 PM PDT 24	Mar 21 04:34:17 PM PDT 24	5806802458 ps
T154	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2567256512			Mar 21 04:00:32 PM PDT 24	Mar 21 04:19:53 PM PDT 24	5614146232 ps
T607	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630359308			Mar 21 04:30:13 PM PDT 24	Mar 21 04:36:11 PM PDT 24	3856085616 ps
T799	/workspace/coverage/default/0.chip_sw_uart_smoketest.2403652836			Mar 21 04:01:55 PM PDT 24	Mar 21 04:05:40 PM PDT 24	2653348504 ps
T800	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1309717207			Mar 21 04:12:08 PM PDT 24	Mar 21 04:30:39 PM PDT 24	5625205836 ps
T146	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3325783367			Mar 21 03:57:48 PM PDT 24	Mar 21 04:10:38 PM PDT 24	5769701016 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3055880847			Mar 21 03:58:07 PM PDT 24	Mar 21 04:06:18 PM PDT 24	3636391354 ps
T232	/workspace/coverage/default/1.chip_sw_plic_sw_irq.972757662			Mar 21 04:06:51 PM PDT 24	Mar 21 04:10:38 PM PDT 24	2357179250 ps
T801	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.392209834			Mar 21 03:58:24 PM PDT 24	Mar 21 04:04:33 PM PDT 24	4727481272 ps
T188	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1987047839			Mar 21 04:16:47 PM PDT 24	Mar 21 04:26:08 PM PDT 24	4263447419 ps
T122	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2500420802			Mar 21 04:03:48 PM PDT 24	Mar 21 04:17:24 PM PDT 24	6312626376 ps
T385	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3220292667			Mar 21 04:28:47 PM PDT 24	Mar 21 04:35:12 PM PDT 24	3748993818 ps
T386	/workspace/coverage/default/1.chip_sw_example_rom.2859537591			Mar 21 04:01:29 PM PDT 24	Mar 21 04:03:32 PM PDT 24	2877667240 ps
T365	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.241264792			Mar 21 04:19:32 PM PDT 24	Mar 21 04:50:56 PM PDT 24	8841844142 ps
T13	/workspace/coverage/default/0.chip_sw_gpio_smoketest.598749584			Mar 21 04:03:52 PM PDT 24	Mar 21 04:07:41 PM PDT 24	2900720517 ps
T147	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1280070472			Mar 21 04:18:40 PM PDT 24	Mar 21 04:22:21 PM PDT 24	2396606600 ps
T207	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3641335592			Mar 21 04:03:26 PM PDT 24	Mar 21 04:15:49 PM PDT 24	6100854960 ps
T279	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3305456806			Mar 21 04:01:16 PM PDT 24	Mar 21 04:20:44 PM PDT 24	7519431022 ps
T189	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1388170493			Mar 21 04:04:24 PM PDT 24	Mar 21 04:14:14 PM PDT 24	4527221898 ps
T280	/workspace/coverage/default/40.chip_sw_all_escalation_resets.4012077371			Mar 21 04:27:40 PM PDT 24	Mar 21 04:35:33 PM PDT 24	5302181744 ps
T281	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.460111400			Mar 21 03:58:05 PM PDT 24	Mar 21 04:02:06 PM PDT 24	2864301651 ps
T282	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1302090416			Mar 21 03:57:26 PM PDT 24	Mar 21 04:17:52 PM PDT 24	5623272573 ps
T148	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2077564720			Mar 21 03:59:33 PM PDT 24	Mar 21 04:04:36 PM PDT 24	3302064416 ps
T18	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2740963138			Mar 21 04:01:45 PM PDT 24	Mar 21 04:29:30 PM PDT 24	18998190748 ps
T102	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1584362971			Mar 21 04:07:22 PM PDT 24	Mar 21 04:38:43 PM PDT 24	8884550280 ps
T103	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.867078090			Mar 21 04:03:54 PM PDT 24	Mar 21 04:17:48 PM PDT 24	5355209144 ps
T104	/workspace/coverage/default/1.chip_sw_aes_masking_off.1644899404			Mar 21 04:05:06 PM PDT 24	Mar 21 04:09:06 PM PDT 24	2624351736 ps
T6	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2085412971			Mar 21 04:08:32 PM PDT 24	Mar 21 04:20:50 PM PDT 24	11754883568 ps
T105	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2894646417			Mar 21 03:56:43 PM PDT 24	Mar 21 04:21:08 PM PDT 24	7643091770 ps
T106	/workspace/coverage/default/2.chip_sw_plic_sw_irq.31884024			Mar 21 04:17:46 PM PDT 24	Mar 21 04:22:03 PM PDT 24	2665047756 ps
T71	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3753302593			Mar 21 04:01:21 PM PDT 24	Mar 21 04:06:53 PM PDT 24	3020617608 ps
T107	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3741587042			Mar 21 04:02:51 PM PDT 24	Mar 21 04:07:35 PM PDT 24	2625332000 ps
T69	/workspace/coverage/default/2.chip_jtag_mem_access.571589304			Mar 21 04:11:20 PM PDT 24	Mar 21 04:39:20 PM PDT 24	12689786100 ps
T332	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.117416781			Mar 21 04:10:35 PM PDT 24	Mar 21 04:13:21 PM PDT 24	2446392212 ps
T614	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1070305377			Mar 21 04:29:52 PM PDT 24	Mar 21 04:35:32 PM PDT 24	3987024308 ps
T137	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3414918888			Mar 21 04:16:08 PM PDT 24	Mar 21 04:23:53 PM PDT 24	5094388766 ps
T110	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3198724373			Mar 21 04:10:52 PM PDT 24	Mar 21 05:05:48 PM PDT 24	25035927492 ps
T608	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2148521024			Mar 21 04:27:06 PM PDT 24	Mar 21 04:33:38 PM PDT 24	3838966324 ps
T301	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3214311488			Mar 21 03:56:31 PM PDT 24	Mar 21 04:13:46 PM PDT 24	12625090157 ps
T138	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2600780796			Mar 21 04:17:52 PM PDT 24	Mar 21 04:28:30 PM PDT 24	4503260530 ps
T324	/workspace/coverage/default/0.chip_sw_aon_timer_irq.3461114467			Mar 21 03:58:59 PM PDT 24	Mar 21 04:07:36 PM PDT 24	4459547896 ps
T318	/workspace/coverage/default/31.chip_sw_all_escalation_resets.3658272650			Mar 21 04:26:33 PM PDT 24	Mar 21 04:37:20 PM PDT 24	4598587260 ps
T802	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.4098377646			Mar 21 04:00:56 PM PDT 24	Mar 21 04:06:20 PM PDT 24	2655538284 ps
T37	/workspace/coverage/default/1.chip_sw_spi_device_tpm.2974803271			Mar 21 04:02:39 PM PDT 24	Mar 21 04:08:12 PM PDT 24	3336040294 ps
T40	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2247167744			Mar 21 04:08:49 PM PDT 24	Mar 21 04:34:12 PM PDT 24	7535090716 ps
T634	/workspace/coverage/default/0.chip_sw_hmac_smoketest.206862406			Mar 21 04:00:51 PM PDT 24	Mar 21 04:06:06 PM PDT 24	2999225224 ps
T319	/workspace/coverage/default/4.chip_sw_all_escalation_resets.3127856947			Mar 21 04:21:38 PM PDT 24	Mar 21 04:31:43 PM PDT 24	4525252698 ps
T63	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1244443522			Mar 21 04:24:00 PM PDT 24	Mar 21 04:30:10 PM PDT 24	5208301127 ps
T194	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3047135650			Mar 21 04:07:06 PM PDT 24	Mar 21 04:13:38 PM PDT 24	4413812328 ps
T803	/workspace/coverage/default/1.chip_sw_aes_entropy.2948771908			Mar 21 04:05:27 PM PDT 24	Mar 21 04:10:03 PM PDT 24	2575826168 ps
T662	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.629687225			Mar 21 04:23:02 PM PDT 24	Mar 21 04:29:36 PM PDT 24	3436341494 ps
T160	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2263023938			Mar 21 03:57:06 PM PDT 24	Mar 21 04:11:35 PM PDT 24	3715601256 ps
T804	/workspace/coverage/default/0.chip_sw_csrng_kat_test.1227549243			Mar 21 04:00:49 PM PDT 24	Mar 21 04:05:19 PM PDT 24	2690432392 ps
T366	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4264198117			Mar 21 04:18:02 PM PDT 24	Mar 21 04:35:33 PM PDT 24	5482721413 ps
T131	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.4091113182			Mar 21 04:04:06 PM PDT 24	Mar 21 04:28:51 PM PDT 24	7915778000 ps
T47	/workspace/coverage/default/1.chip_jtag_csr_rw.3724021599			Mar 21 04:02:03 PM PDT 24	Mar 21 04:24:33 PM PDT 24	11902732704 ps
T370	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3284234963			Mar 21 04:07:01 PM PDT 24	Mar 21 04:11:35 PM PDT 24	3405021388 ps
T371	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.611674066			Mar 21 04:27:04 PM PDT 24	Mar 21 04:32:55 PM PDT 24	3402899376 ps
T190	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3137353279			Mar 21 04:16:02 PM PDT 24	Mar 21 04:23:26 PM PDT 24	3101895606 ps
T372	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3855242554			Mar 21 04:04:56 PM PDT 24	Mar 21 04:08:11 PM PDT 24	3309519590 ps
T373	/workspace/coverage/default/2.chip_sw_otbn_smoketest.477514268			Mar 21 04:20:31 PM PDT 24	Mar 21 04:42:05 PM PDT 24	7492979656 ps
T156	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1163975322			Mar 21 04:02:23 PM PDT 24	Mar 21 04:12:16 PM PDT 24	5420092683 ps
T374	/workspace/coverage/default/2.chip_sw_kmac_app_rom.3382798092			Mar 21 04:16:32 PM PDT 24	Mar 21 04:19:58 PM PDT 24	2678575174 ps
T375	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2299716614			Mar 21 04:15:41 PM PDT 24	Mar 21 04:21:41 PM PDT 24	4469722584 ps
T376	/workspace/coverage/default/1.chip_sw_kmac_smoketest.4181620929			Mar 21 04:12:54 PM PDT 24	Mar 21 04:18:03 PM PDT 24	3202296728 ps
T695	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.397544626			Mar 21 04:27:31 PM PDT 24	Mar 21 04:34:43 PM PDT 24	4128869480 ps
T187	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2173695358			Mar 21 04:14:54 PM PDT 24	Mar 21 07:47:18 PM PDT 24	77220925102 ps
T157	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.695846296			Mar 21 04:17:56 PM PDT 24	Mar 21 04:28:33 PM PDT 24	4611904520 ps
T313	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3527652894			Mar 21 04:02:05 PM PDT 24	Mar 21 04:05:49 PM PDT 24	2503785580 ps
T128	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1857604327			Mar 21 04:26:23 PM PDT 24	Mar 21 04:45:58 PM PDT 24	7369280267 ps
T661	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3022740222			Mar 21 04:28:42 PM PDT 24	Mar 21 04:36:50 PM PDT 24	3446572470 ps
T610	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.744456144			Mar 21 04:19:35 PM PDT 24	Mar 21 04:26:11 PM PDT 24	3239561708 ps
T395	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3209723026			Mar 21 04:26:16 PM PDT 24	Mar 21 04:38:09 PM PDT 24	5673575634 ps
T224	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3905298290			Mar 21 04:26:03 PM PDT 24	Mar 21 04:32:21 PM PDT 24	3524512880 ps
T606	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1489039503			Mar 21 04:25:55 PM PDT 24	Mar 21 04:32:15 PM PDT 24	3386748472 ps
T195	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.2020901594			Mar 21 04:14:15 PM PDT 24	Mar 21 07:13:25 PM PDT 24	63426037719 ps
T193	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1544278175			Mar 21 04:24:00 PM PDT 24	Mar 21 04:36:23 PM PDT 24	5691519493 ps
T311	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3540358038			Mar 21 04:23:12 PM PDT 24	Mar 21 04:32:01 PM PDT 24	5567403544 ps
T805	/workspace/coverage/default/0.rom_e2e_asm_init_dev.3317320875			Mar 21 04:07:30 PM PDT 24	Mar 21 04:42:04 PM PDT 24	9428726581 ps
T806	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1327285460			Mar 21 04:10:12 PM PDT 24	Mar 21 04:30:08 PM PDT 24	7633843647 ps
T7	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.137451838			Mar 21 04:02:45 PM PDT 24	Mar 21 04:07:20 PM PDT 24	3503625587 ps
T125	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1801514636			Mar 21 03:57:07 PM PDT 24	Mar 21 03:59:14 PM PDT 24	2641772291 ps
T284	/workspace/coverage/default/1.chip_plic_all_irqs_20.3500892113			Mar 21 04:07:54 PM PDT 24	Mar 21 04:21:00 PM PDT 24	4798581800 ps
T291	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.521914998			Mar 21 03:56:27 PM PDT 24	Mar 21 04:07:01 PM PDT 24	4440562080 ps
T38	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2380295085			Mar 21 03:58:12 PM PDT 24	Mar 21 04:06:05 PM PDT 24	3539732000 ps
T11	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3584473676			Mar 21 03:58:00 PM PDT 24	Mar 21 04:07:31 PM PDT 24	4188115558 ps
T396	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2026198598			Mar 21 04:05:41 PM PDT 24	Mar 21 04:10:52 PM PDT 24	3692862060 ps
T302	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1198382366			Mar 21 04:23:53 PM PDT 24	Mar 21 04:33:59 PM PDT 24	4987097620 ps
T615	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.263237711			Mar 21 03:58:24 PM PDT 24	Mar 21 04:03:49 PM PDT 24	3444872500 ps
T78	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.680349680			Mar 21 04:16:48 PM PDT 24	Mar 21 04:36:46 PM PDT 24	12174382714 ps
T807	/workspace/coverage/default/0.chip_sw_kmac_idle.1292296915			Mar 21 03:58:19 PM PDT 24	Mar 21 04:03:10 PM PDT 24	3064480326 ps
T808	/workspace/coverage/default/0.chip_sw_example_rom.1047490829			Mar 21 03:57:04 PM PDT 24	Mar 21 03:59:12 PM PDT 24	2339962520 ps
T384	/workspace/coverage/default/63.chip_sw_all_escalation_resets.1580598937			Mar 21 04:28:40 PM PDT 24	Mar 21 04:39:05 PM PDT 24	6195271800 ps
T20	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2113601357			Mar 21 04:00:17 PM PDT 24	Mar 21 04:25:44 PM PDT 24	23116346320 ps
T41	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.258407152			Mar 21 04:14:45 PM PDT 24	Mar 21 04:47:21 PM PDT 24	9014370326 ps
T809	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3434880931			Mar 21 04:24:18 PM PDT 24	Mar 21 04:59:15 PM PDT 24	14208621267 ps
T166	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3095273528			Mar 21 04:07:57 PM PDT 24	Mar 21 04:18:57 PM PDT 24	5846117118 ps
T810	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4189714364			Mar 21 04:00:58 PM PDT 24	Mar 21 04:05:48 PM PDT 24	3133578107 ps
T724	/workspace/coverage/default/77.chip_sw_all_escalation_resets.3217762660			Mar 21 04:29:35 PM PDT 24	Mar 21 04:38:33 PM PDT 24	4799367810 ps
T660	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1555725983			Mar 21 04:23:08 PM PDT 24	Mar 21 04:29:36 PM PDT 24	3980062730 ps
T79	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3241398404			Mar 21 04:29:18 PM PDT 24	Mar 21 04:37:23 PM PDT 24	4417851088 ps
T91	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1569711623			Mar 21 04:20:54 PM PDT 24	Mar 21 04:26:23 PM PDT 24	3274301350 ps
T92	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3324671506			Mar 21 04:02:01 PM PDT 24	Mar 21 04:10:22 PM PDT 24	5943253486 ps
T93	/workspace/coverage/default/1.rom_e2e_asm_init_rma.4275081045			Mar 21 04:15:27 PM PDT 24	Mar 21 04:48:27 PM PDT 24	9317714332 ps
T94	/workspace/coverage/default/2.rom_e2e_static_critical.2272184741			Mar 21 04:23:58 PM PDT 24	Mar 21 05:01:00 PM PDT 24	11186970060 ps
T95	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1140084653			Mar 21 04:08:32 PM PDT 24	Mar 21 04:20:21 PM PDT 24	4186965844 ps
T96	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2984268412			Mar 21 04:23:31 PM PDT 24	Mar 21 05:11:42 PM PDT 24	23204160549 ps
T97	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.720783292			Mar 21 04:16:29 PM PDT 24	Mar 21 04:34:07 PM PDT 24	6232146346 ps
T14	/workspace/coverage/default/2.chip_sw_gpio_smoketest.2691796411			Mar 21 04:21:23 PM PDT 24	Mar 21 04:26:39 PM PDT 24	3323860504 ps
T98	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1997910234			Mar 21 04:10:01 PM PDT 24	Mar 21 04:17:25 PM PDT 24	6286056584 ps
T165	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2272274998			Mar 21 04:22:02 PM PDT 24	Mar 21 04:37:55 PM PDT 24	7424603784 ps
T210	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2412322535			Mar 21 04:15:59 PM PDT 24	Mar 21 04:23:47 PM PDT 24	4811728584 ps
T811	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2287074425			Mar 21 04:07:42 PM PDT 24	Mar 21 04:16:29 PM PDT 24	4751012352 ps
T140	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3218777662			Mar 21 04:23:14 PM PDT 24	Mar 21 04:39:39 PM PDT 24	11973670413 ps
T381	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1316384665			Mar 21 04:24:57 PM PDT 24	Mar 21 04:30:19 PM PDT 24	2557749480 ps
T65	/workspace/coverage/default/1.chip_tap_straps_rma.208368785			Mar 21 04:08:43 PM PDT 24	Mar 21 04:15:18 PM PDT 24	5156159829 ps
T358	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.903982451			Mar 21 04:18:19 PM PDT 24	Mar 21 04:40:17 PM PDT 24	10497059644 ps
T679	/workspace/coverage/default/44.chip_sw_all_escalation_resets.4275206042			Mar 21 04:26:50 PM PDT 24	Mar 21 04:37:49 PM PDT 24	5654197866 ps
T211	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3259058550			Mar 21 04:18:30 PM PDT 24	Mar 21 04:30:04 PM PDT 24	4304433070 ps
T129	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3826693757			Mar 21 04:06:55 PM PDT 24	Mar 21 04:46:48 PM PDT 24	9920070768 ps
T134	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3355601137			Mar 21 04:14:32 PM PDT 24	Mar 21 04:22:49 PM PDT 24	3841334029 ps
T167	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2457022366			Mar 21 04:18:38 PM PDT 24	Mar 21 04:26:41 PM PDT 24	5025941950 ps
T158	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2783781261			Mar 21 04:10:13 PM PDT 24	Mar 21 04:22:46 PM PDT 24	4248883316 ps
T812	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3680800615			Mar 21 04:01:58 PM PDT 24	Mar 21 04:14:00 PM PDT 24	5252175600 ps
T246	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2434214193			Mar 21 04:06:09 PM PDT 24	Mar 21 04:38:05 PM PDT 24	8009436291 ps
T130	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.4223645976			Mar 21 04:05:05 PM PDT 24	Mar 21 04:33:36 PM PDT 24	7158489165 ps
T593	/workspace/coverage/default/33.chip_sw_all_escalation_resets.3097233367			Mar 21 04:26:07 PM PDT 24	Mar 21 04:37:49 PM PDT 24	5032736890 ps
T320	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1187959745			Mar 21 04:27:46 PM PDT 24	Mar 21 04:36:13 PM PDT 24	5162694606 ps
T350	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.807968591			Mar 21 03:57:59 PM PDT 24	Mar 21 04:04:18 PM PDT 24	5531841180 ps
T351	/workspace/coverage/default/2.chip_sw_csrng_smoketest.2799798200			Mar 21 04:20:23 PM PDT 24	Mar 21 04:24:11 PM PDT 24	2873323272 ps
T352	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3270088473			Mar 21 04:17:22 PM PDT 24	Mar 21 04:28:51 PM PDT 24	7998099158 ps
T186	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4182935130			Mar 21 04:04:01 PM PDT 24	Mar 21 04:47:20 PM PDT 24	22913405043 ps
T353	/workspace/coverage/default/1.chip_sw_all_escalation_resets.4046267527			Mar 21 04:03:36 PM PDT 24	Mar 21 04:13:28 PM PDT 24	5209227320 ps
T111	/workspace/coverage/default/2.rom_raw_unlock.370107505			Mar 21 04:22:21 PM PDT 24	Mar 21 04:49:30 PM PDT 24	15290172554 ps
T314	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2622179941			Mar 21 04:00:26 PM PDT 24	Mar 21 04:04:04 PM PDT 24	2318189688 ps
T354	/workspace/coverage/default/0.rom_e2e_asm_init_rma.791548949			Mar 21 04:04:35 PM PDT 24	Mar 21 04:36:06 PM PDT 24	8699291014 ps
T355	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2301601028			Mar 21 04:23:04 PM PDT 24	Mar 21 05:21:06 PM PDT 24	23457200580 ps
T212	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2021047847			Mar 21 04:16:12 PM PDT 24	Mar 21 05:00:42 PM PDT 24	12666384144 ps
T124	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1543072335			Mar 21 04:14:47 PM PDT 24	Mar 21 04:16:50 PM PDT 24	2553118264 ps
T86	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.703768666			Mar 21 04:29:54 PM PDT 24	Mar 21 04:36:37 PM PDT 24	3394853864 ps
T696	/workspace/coverage/default/97.chip_sw_all_escalation_resets.76531657			Mar 21 04:30:25 PM PDT 24	Mar 21 04:40:21 PM PDT 24	4654788200 ps
T247	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.4083473998			Mar 21 04:05:42 PM PDT 24	Mar 21 04:52:05 PM PDT 24	11817193916 ps
T655	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1560266021			Mar 21 04:25:51 PM PDT 24	Mar 21 04:37:11 PM PDT 24	5576939608 ps
T813	/workspace/coverage/default/0.rom_e2e_asm_init_prod.3799912372			Mar 21 04:07:10 PM PDT 24	Mar 21 04:42:17 PM PDT 24	8490018409 ps
T814	/workspace/coverage/default/1.chip_sw_uart_smoketest.3702080177			Mar 21 04:14:24 PM PDT 24	Mar 21 04:19:19 PM PDT 24	2970413488 ps
T815	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3289145096			Mar 21 04:12:14 PM PDT 24	Mar 21 04:17:41 PM PDT 24	2846751974 ps
T19	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2029459585			Mar 21 04:05:11 PM PDT 24	Mar 21 04:12:16 PM PDT 24	5386451000 ps
T191	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.629903567			Mar 21 04:05:49 PM PDT 24	Mar 21 04:16:42 PM PDT 24	5364213946 ps
T73	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2907213135			Mar 21 04:13:09 PM PDT 24	Mar 21 04:18:51 PM PDT 24	4592800272 ps
T659	/workspace/coverage/default/86.chip_sw_all_escalation_resets.1187092362			Mar 21 04:29:58 PM PDT 24	Mar 21 04:37:22 PM PDT 24	5340905928 ps
T816	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3604598056			Mar 21 04:04:51 PM PDT 24	Mar 21 04:19:14 PM PDT 24	9330208374 ps
T817	/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.3864369062			Mar 21 04:17:55 PM PDT 24	Mar 21 04:46:59 PM PDT 24	8594757382 ps
T149	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3618272600			Mar 21 04:19:03 PM PDT 24	Mar 21 04:21:57 PM PDT 24	2424259211 ps
T141	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.276780604			Mar 21 04:03:39 PM PDT 24	Mar 21 04:05:43 PM PDT 24	2801420774 ps
T8	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1499326395			Mar 21 04:00:11 PM PDT 24	Mar 21 04:04:28 PM PDT 24	2789392629 ps
T126	/workspace/coverage/default/0.rom_volatile_raw_unlock.3561012666			Mar 21 04:03:31 PM PDT 24	Mar 21 04:05:30 PM PDT 24	2093326619 ps
T818	/workspace/coverage/default/2.chip_sw_aes_enc.3743401131			Mar 21 04:15:15 PM PDT 24	Mar 21 04:18:57 PM PDT 24	2411115786 ps
T819	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1074902834			Mar 21 04:13:57 PM PDT 24	Mar 21 04:43:38 PM PDT 24	23574370942 ps
T820	/workspace/coverage/default/1.rom_keymgr_functest.1841052461			Mar 21 04:14:03 PM PDT 24	Mar 21 04:26:17 PM PDT 24	4672098480 ps
T821	/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.701468507			Mar 21 04:26:03 PM PDT 24	Mar 21 04:55:03 PM PDT 24	8624000354 ps
T309	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1131780530			Mar 21 04:24:39 PM PDT 24	Mar 21 04:35:09 PM PDT 24	3963004700 ps
T233	/workspace/coverage/default/1.chip_sw_rv_timer_irq.49923610			Mar 21 04:04:07 PM PDT 24	Mar 21 04:07:53 PM PDT 24	2963526834 ps
T135	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.731009630			Mar 21 04:05:26 PM PDT 24	Mar 21 04:10:57 PM PDT 24	3830060682 ps
T142	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1637114624			Mar 21 03:58:37 PM PDT 24	Mar 21 04:01:25 PM PDT 24	3469364655 ps
T161	/workspace/coverage/default/2.chip_sw_edn_auto_mode.380819963			Mar 21 04:22:42 PM PDT 24	Mar 21 04:42:17 PM PDT 24	6458986444 ps
T822	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1818156227			Mar 21 04:25:31 PM PDT 24	Mar 21 04:34:54 PM PDT 24	4678228212 ps
T823	/workspace/coverage/default/1.chip_sw_csrng_smoketest.719471894			Mar 21 04:14:16 PM PDT 24	Mar 21 04:17:37 PM PDT 24	2329232316 ps
T824	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1869358521			Mar 21 04:02:54 PM PDT 24	Mar 21 04:11:09 PM PDT 24	6665390008 ps
T825	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1685364297			Mar 21 04:00:58 PM PDT 24	Mar 21 04:09:47 PM PDT 24	4359821166 ps
T201	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3568840312			Mar 21 04:22:37 PM PDT 24	Mar 21 04:37:57 PM PDT 24	12335488227 ps
T720	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.598965894			Mar 21 04:26:48 PM PDT 24	Mar 21 04:35:05 PM PDT 24	3967985018 ps
T826	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2884607231			Mar 21 04:16:32 PM PDT 24	Mar 21 04:25:17 PM PDT 24	5419382274 ps
T622	/workspace/coverage/default/2.chip_sw_power_idle_load.1240435803			Mar 21 04:20:22 PM PDT 24	Mar 21 04:31:44 PM PDT 24	3990920290 ps
T827	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1320449620			Mar 21 04:21:55 PM PDT 24	Mar 21 04:30:22 PM PDT 24	4391474638 ps
T259	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1425239222			Mar 21 03:59:19 PM PDT 24	Mar 21 04:10:02 PM PDT 24	3788658218 ps
T654	/workspace/coverage/default/99.chip_sw_all_escalation_resets.3422189429			Mar 21 04:30:05 PM PDT 24	Mar 21 04:40:09 PM PDT 24	4758954950 ps
T828	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.581232892			Mar 21 04:18:32 PM PDT 24	Mar 21 04:22:14 PM PDT 24	2626420790 ps
T594	/workspace/coverage/default/15.chip_sw_all_escalation_resets.4175164264			Mar 21 04:25:05 PM PDT 24	Mar 21 04:34:26 PM PDT 24	4365285432 ps
T829	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.4166392533			Mar 21 04:22:01 PM PDT 24	Mar 21 04:34:55 PM PDT 24	5601640121 ps
T830	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.556811332			Mar 21 04:05:12 PM PDT 24	Mar 21 04:09:31 PM PDT 24	2183700010 ps
T612	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3531441206			Mar 21 04:27:13 PM PDT 24	Mar 21 04:39:00 PM PDT 24	4915103918 ps
T721	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2615691276			Mar 21 04:27:41 PM PDT 24	Mar 21 04:32:40 PM PDT 24	3276344830 ps
T343	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4011645739			Mar 21 04:06:31 PM PDT 24	Mar 21 04:52:07 PM PDT 24	12104732200 ps
T831	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3701169073			Mar 21 04:05:15 PM PDT 24	Mar 21 04:50:11 PM PDT 24	11302597637 ps
T23	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2375468390			Mar 21 03:58:27 PM PDT 24	Mar 21 05:49:41 PM PDT 24	31208280974 ps
T24	/workspace/coverage/default/2.chip_jtag_csr_rw.2759317533			Mar 21 04:11:12 PM PDT 24	Mar 21 04:29:36 PM PDT 24	11063161280 ps
T605	/workspace/coverage/default/64.chip_sw_all_escalation_resets.442762722			Mar 21 04:28:05 PM PDT 24	Mar 21 04:37:06 PM PDT 24	4832565064 ps
T197	/workspace/coverage/default/1.chip_sw_uart_tx_rx.1712055495			Mar 21 04:03:00 PM PDT 24	Mar 21 04:20:08 PM PDT 24	5517986121 ps
T611	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2326183819			Mar 21 04:24:02 PM PDT 24	Mar 21 04:37:13 PM PDT 24	5670493026 ps
T213	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2507667336			Mar 21 03:57:37 PM PDT 24	Mar 21 05:08:28 PM PDT 24	17194896872 ps
T390	/workspace/coverage/default/0.chip_jtag_mem_access.348493695			Mar 21 03:51:12 PM PDT 24	Mar 21 04:11:33 PM PDT 24	13116443032 ps
T832	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.507586048			Mar 21 04:23:47 PM PDT 24	Mar 21 04:52:04 PM PDT 24	12363397681 ps