Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3740	1			T400	14		T492	2		T401	1
all_values[1]	3677	1			T400	8		T401	3		T486	5
all_values[2]	3728	1			T400	9		T492	3		T401	2
all_values[3]	3686	1			T74	1		T400	13		T492	2
all_values[4]	3874	1			T400	10		T492	1		T401	4
all_values[5]	3824	1			T74	2		T400	16		T492	4
all_values[6]	3791	1			T400	6		T492	2		T401	2
all_values[7]	3724	1			T400	11		T492	3		T401	2
all_values[8]	3707	1			T400	15		T492	1		T401	3
all_values[9]	3653	1			T400	11		T492	3		T401	3
all_values[10]	3711	1			T74	2		T400	9		T492	1
all_values[11]	3745	1			T400	6		T492	2		T401	4
all_values[12]	3814	1			T400	11		T401	2		T486	3
all_values[13]	3789	1			T74	2		T400	12		T492	5
all_values[14]	3782	1			T400	10		T492	1		T401	1
all_values[15]	3747	1			T74	1		T400	9		T492	5
all_values[16]	3712	1			T400	10		T492	2		T401	1
all_values[17]	3676	1			T400	7		T492	2		T401	1
all_values[18]	3705	1			T74	1		T400	13		T492	2
all_values[19]	3704	1			T400	14		T492	3		T401	4
all_values[20]	3769	1			T400	10		T492	1		T401	3
all_values[21]	3760	1			T400	10		T492	4		T401	3
all_values[22]	3660	1			T400	16		T492	2		T401	3
all_values[23]	3803	1			T74	2		T400	10		T492	3
all_values[24]	3766	1			T74	1		T400	22		T401	2
all_values[25]	3718	1			T400	11		T492	2		T401	3
all_values[26]	3665	1			T400	19		T492	1		T401	5
all_values[27]	3673	1			T400	3		T492	4		T401	4
all_values[28]	3687	1			T74	1		T400	8		T492	5
all_values[29]	3695	1			T74	1		T400	12		T492	7
all_values[30]	3745	1			T400	11		T492	6		T401	3
all_values[31]	3680	1			T74	1		T400	15		T492	2
all_values[32]	3710	1			T400	13		T492	4		T485	27
all_values[33]	3656	1			T400	14		T492	4		T401	3
all_values[34]	3699	1			T74	1		T400	11		T492	5
all_values[35]	3680	1			T400	6		T492	1		T401	2
all_values[36]	3785	1			T400	9		T492	1		T401	1
all_values[37]	3809	1			T400	15		T492	1		T401	2
all_values[38]	3756	1			T74	1		T400	8		T492	7
all_values[39]	3740	1			T400	7		T492	1		T401	1
all_values[40]	3727	1			T400	15		T492	5		T485	24
all_values[41]	3756	1			T400	12		T492	4		T401	2
all_values[42]	3652	1			T74	1		T400	10		T492	1
all_values[43]	3727	1			T400	6		T492	2		T401	4
all_values[44]	3766	1			T400	12		T492	2		T401	1
all_values[45]	3781	1			T74	1		T400	14		T492	4
all_values[46]	3730	1			T74	1		T400	9		T492	1
all_values[47]	3689	1			T400	10		T492	3		T401	3
all_values[48]	3670	1			T74	1		T400	5		T492	4
all_values[49]	3673	1			T400	3		T492	5		T401	7
all_values[50]	3757	1			T400	8		T492	4		T401	1
all_values[51]	3773	1			T74	1		T400	8		T492	2
all_values[52]	3818	1			T74	1		T400	13		T492	1
all_values[53]	3702	1			T400	5		T492	1		T401	2
all_values[54]	3569	1			T74	1		T400	6		T492	2
all_values[55]	3827	1			T400	18		T492	2		T401	1
all_values[56]	3707	1			T74	1		T400	14		T492	2
all_values[57]	3641	1			T400	10		T492	2		T401	4
all_values[58]	3751	1			T400	5		T492	2		T401	3
all_values[59]	3760	1			T400	13		T401	1		T486	2
all_values[60]	3790	1			T400	17		T492	3		T401	1
all_values[61]	3635	1			T400	9		T492	2		T486	1
all_values[62]	3683	1			T400	15		T492	3		T401	2
all_values[63]	3785	1			T74	1		T400	13		T492	1