Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145456	1			T72	80		T73	54		T74	6
values[2]	10172	1			T72	4		T73	7		T510	1
values[3]	3741	1			T686	1		T421	21		T508	1
values[4]	2258	1			T686	1		T421	4		T592	33
values[5]	1324	1			T686	1		T592	15		T623	2
values[6]	797	1			T686	1		T592	5		T623	1
values[7]	625	1			T686	1		T592	4		T623	3
values[8]	554	1			T686	1		T592	9		T458	1
values[9]	411	1			T686	1		T592	9		T458	1
values[10]	424	1			T686	1		T592	11		T458	1
values[11]	392	1			T686	1		T592	8		T458	1
values[12]	290	1			T686	1		T592	10		T458	1
values[13]	284	1			T686	1		T592	5		T458	1
values[14]	352	1			T686	1		T592	4		T458	1
values[15]	325	1			T686	1		T592	3		T458	1
values[16]	234	1			T686	1		T592	11		T458	1
values[17]	247	1			T686	1		T592	13		T458	1
values[18]	296	1			T686	1		T592	8		T458	1
values[19]	293	1			T686	1		T592	3		T458	1
values[20]	318	1			T686	1		T592	21		T458	1
values[21]	324	1			T686	1		T592	7		T458	2
values[22]	290	1			T686	1		T592	5		T458	1
values[23]	290	1			T686	1		T592	6		T458	1
values[24]	280	1			T686	1		T592	7		T458	1
values[25]	284	1			T686	1		T592	4		T458	1
values[26]	243	1			T686	1		T592	4		T458	1
values[27]	265	1			T686	1		T592	7		T458	1
values[28]	260	1			T686	1		T592	2		T458	1
values[29]	305	1			T686	1		T592	5		T458	1
values[30]	311	1			T686	1		T592	19		T458	1
values[31]	312	1			T686	1		T592	16		T458	1
values[32]	268	1			T686	1		T592	10		T458	1
values[33]	283	1			T686	1		T592	15		T458	1
values[34]	284	1			T686	1		T592	7		T458	2
values[35]	270	1			T686	1		T592	7		T458	1
values[36]	313	1			T686	1		T592	2		T458	1
values[37]	311	1			T686	1		T592	5		T458	1
values[38]	280	1			T686	1		T592	7		T458	1
values[39]	267	1			T686	1		T592	4		T458	1
values[40]	337	1			T686	1		T592	3		T458	1
values[41]	272	1			T686	1		T592	8		T458	1
values[42]	286	1			T686	1		T592	5		T458	1
values[43]	309	1			T686	1		T592	19		T458	1
values[44]	275	1			T686	1		T592	2		T458	1
values[45]	273	1			T686	1		T592	11		T458	1
values[46]	252	1			T686	1		T592	4		T458	1
values[47]	243	1			T686	1		T592	4		T458	1
values[48]	288	1			T686	1		T592	13		T458	1
values[49]	217	1			T686	1		T592	3		T458	1
values[50]	246	1			T686	1		T592	2		T458	1
values[51]	253	1			T686	1		T592	7		T458	1
values[52]	244	1			T686	1		T592	3		T458	1
values[53]	226	1			T686	1		T592	10		T458	1
values[54]	229	1			T686	1		T592	7		T458	1
values[55]	215	1			T686	1		T592	12		T458	1
values[56]	209	1			T686	1		T592	4		T458	1
values[57]	230	1			T686	1		T592	6		T458	1
values[58]	252	1			T686	1		T592	10		T458	1
values[59]	272	1			T686	1		T458	1		T760	7
values[60]	225	1			T686	1		T458	1		T760	5
values[61]	224	1			T686	1		T458	1		T760	7
values[62]	238	1			T686	1		T458	1		T760	7
values[63]	198	1			T686	1		T458	1		T760	10
values[64]	224	1			T686	1		T458	1		T760	9
values[65]	210	1			T686	1		T458	1		T760	11
values[66]	202	1			T686	1		T458	1		T760	12
values[67]	203	1			T686	1		T458	1		T760	4
values[68]	161	1			T686	1		T458	1		T760	5
values[69]	160	1			T686	1		T458	1		T760	4
values[70]	153	1			T686	1		T458	1		T760	12
values[71]	153	1			T686	1		T458	1		T760	15
values[72]	138	1			T686	1		T458	1		T760	16
values[73]	121	1			T686	1		T458	1		T760	7
values[74]	108	1			T686	1		T458	1		T760	13
values[75]	72	1			T686	1		T458	1		T777	11
values[76]	81	1			T686	1		T458	1		T777	9
values[77]	97	1			T686	1		T458	1		T777	13
values[78]	108	1			T686	1		T458	1		T777	11
values[79]	99	1			T686	1		T458	1		T777	8
values[80]	72	1			T686	1		T458	1		T777	3
values[81]	85	1			T686	1		T458	1		T801	7
values[82]	88	1			T686	1		T458	1		T801	8
values[83]	67	1			T686	1		T458	1		T801	7
values[84]	80	1			T686	1		T458	1		T801	8
values[85]	69	1			T686	1		T458	1		T801	10
values[86]	78	1			T686	1		T458	1		T801	9
values[87]	76	1			T686	1		T458	1		T801	14
values[88]	90	1			T686	1		T458	1		T801	6
values[89]	78	1			T686	1		T458	1		T801	6
values[90]	67	1			T686	1		T458	1		T801	14
values[91]	74	1			T686	1		T458	1		T801	7
values[92]	63	1			T686	1		T458	6		T801	3
values[93]	62	1			T686	1		T458	1		T801	5
values[94]	80	1			T686	2		T458	3		T801	12
values[95]	83	1			T686	1		T458	3		T801	16
values[96]	63	1			T686	1		T458	2		T801	11
values[97]	70	1			T686	1		T458	1		T801	12
values[98]	76	1			T686	1		T458	3		T801	14
values[99]	78	1			T686	1		T458	3		T801	10
values[100]	78	1			T686	1		T458	7		T801	11
values[101]	86	1			T686	1		T458	1		T801	13
values[102]	69	1			T686	1		T458	3		T801	4
values[103]	69	1			T686	1		T458	1		T801	4
values[104]	84	1			T686	1		T458	4		T801	13
values[105]	69	1			T686	2		T458	1		T801	14
values[106]	68	1			T686	1		T458	1		T801	8
values[107]	81	1			T686	1		T458	2		T801	11
values[108]	66	1			T686	1		T458	3		T801	7
values[109]	66	1			T686	1		T458	1		T801	10
values[110]	61	1			T686	1		T458	3		T801	13
values[111]	78	1			T686	1		T458	2		T801	13
values[112]	74	1			T686	1		T458	1		T801	8
values[113]	58	1			T686	1		T458	2		T801	9
values[114]	75	1			T686	1		T458	1		T801	15
values[115]	69	1			T686	1		T458	1		T801	8
values[116]	92	1			T686	1		T458	1		T801	11
values[117]	88	1			T686	3		T458	2		T801	20
values[118]	78	1			T686	3		T458	4		T801	13
values[119]	64	1			T686	5		T458	2		T801	11
values[120]	44	1			T686	1		T458	1		T801	7
values[121]	36	1			T686	1		T458	1		T801	4
values[122]	49	1			T686	1		T458	1		T801	7
values[123]	65	1			T686	2		T458	3		T801	7
values[124]	56	1			T686	1		T458	1		T801	6
values[125]	98	1			T686	1		T458	1		T801	2
values[126]	170	1			T686	3		T458	2		T801	10
values[127]	773	1			T686	22		T458	25		T801	25
values[128]	4828	1			T686	311		T458	289		T801	14