Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.19	95.38	94.18	95.66		94.94	97.38	99.58

Total tests in report: 2838

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
41.90	41.90	46.79	46.79	45.10	45.10	35.93	35.93			59.73	59.73	63.03	63.03	0.81	0.81	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1761504413
53.97	12.07	57.71	10.93	62.69	17.58	40.54	4.60			71.39	11.65	89.65	26.62	1.87	1.06	/workspace/coverage/cover_reg_top/4.chip_csr_rw.3655373997
60.20	6.22	62.28	4.57	63.59	0.90	41.63	1.10			71.39	0.00	89.65	0.00	32.65	30.78	/workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2806532672
65.92	5.72	72.86	10.58	70.91	7.33	47.79	6.16			81.16	9.77	90.02	0.37	32.78	0.13	/workspace/coverage/default/0.chip_jtag_csr_rw.579379369
68.72	2.80	72.86	0.00	71.15	0.24	47.79	0.00			81.19	0.03	90.02	0.00	49.32	16.54	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2249854519
71.08	2.36	72.86	0.00	71.15	0.00	61.93	14.14			81.19	0.00	90.02	0.00	49.32	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.374020249
73.42	2.34	78.19	5.33	74.93	3.78	65.36	3.43			82.70	1.51	90.02	0.00	49.32	0.00	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1692683330
75.69	2.27	78.19	0.01	75.63	0.69	66.06	0.70			82.73	0.03	90.02	0.00	61.52	12.20	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2898692573
77.45	1.76	81.60	3.41	77.76	2.13	68.57	2.51			85.23	2.50	90.02	0.00	61.52	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2495226587
79.14	1.69	85.24	3.63	78.21	0.45	70.31	1.74			85.29	0.07	90.02	0.00	65.76	4.24	/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3466602610
80.78	1.64	85.24	0.00	78.21	0.00	70.31	0.00			85.29	0.00	90.02	0.00	75.62	9.86	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3315222313
82.27	1.49	85.32	0.09	78.22	0.01	78.96	8.65			85.30	0.01	90.20	0.18	75.62	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2139100924
83.63	1.35	87.22	1.89	80.35	2.12	79.67	0.71			87.48	2.18	91.31	1.11	75.73	0.11	/workspace/coverage/default/2.chip_jtag_csr_rw.844094730
84.86	1.23	87.22	0.00	80.35	0.00	79.67	0.00			87.48	0.00	91.31	0.00	83.12	7.39	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3999257038
85.79	0.94	87.32	0.11	80.35	0.01	85.17	5.50			87.48	0.00	91.31	0.00	83.12	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.4065328743
86.61	0.82	88.47	1.15	82.12	1.77	85.40	0.23			89.23	1.75	91.31	0.00	83.12	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1195167991
87.35	0.74	88.63	0.16	82.21	0.09	85.42	0.02			89.32	0.09	95.38	4.07	83.12	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1655075345
88.05	0.70	89.87	1.24	83.25	1.05	86.15	0.73			90.51	1.19	95.38	0.00	83.12	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.160180256
88.73	0.68	89.87	0.00	83.25	0.00	86.15	0.00			90.51	0.00	95.38	0.00	87.22	4.10	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.896435409
89.39	0.66	91.31	1.44	84.41	1.16	86.66	0.51			91.32	0.82	95.38	0.00	87.28	0.06	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3307002595
89.95	0.56	91.31	0.00	84.41	0.00	86.66	0.00			91.32	0.00	95.38	0.00	90.65	3.37	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2608513040
90.48	0.53	92.08	0.77	85.41	1.00	87.26	0.60			92.13	0.81	95.38	0.00	90.65	0.00	/workspace/coverage/default/1.chip_sw_gpio.1682550960
90.92	0.43	92.61	0.53	85.85	0.44	87.84	0.58			92.61	0.48	95.93	0.55	90.65	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4066549508
91.33	0.41	92.62	0.01	87.91	2.06	87.84	0.00			92.61	0.00	95.93	0.00	91.06	0.41	/workspace/coverage/cover_reg_top/21.chip_tl_errors.1468614159
91.70	0.38	93.14	0.52	88.42	0.51	88.48	0.64			93.00	0.39	96.12	0.18	91.07	0.01	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3564284800
92.07	0.37	93.14	0.00	88.42	0.00	89.50	1.02			93.00	0.00	96.12	0.00	92.25	1.17	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1785397210
92.43	0.36	93.14	0.00	88.42	0.00	89.50	0.00			93.00	0.00	96.12	0.00	94.41	2.16	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1359852847
92.71	0.28	93.63	0.49	88.87	0.44	89.79	0.29			93.44	0.44	96.12	0.00	94.41	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.4021622637
92.95	0.24	93.63	0.00	88.87	0.00	89.79	0.00			93.44	0.00	96.12	0.00	95.86	1.46	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1754545331
93.18	0.23	93.93	0.29	89.71	0.85	89.82	0.02			93.59	0.15	96.12	0.00	95.93	0.07	/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.688389195
93.37	0.18	93.93	0.00	89.71	0.00	90.92	1.11			93.59	0.00	96.12	0.00	95.93	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2687811671
93.52	0.15	94.14	0.22	90.04	0.33	91.28	0.36			93.59	0.00	96.12	0.00	95.93	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2947313657
93.66	0.15	94.19	0.04	90.44	0.40	91.29	0.01			94.02	0.43	96.12	0.00	95.93	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2979600236
93.81	0.14	94.19	0.00	90.58	0.14	91.31	0.02			94.02	0.00	96.12	0.00	96.64	0.70	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3584448158
93.92	0.12	94.19	0.00	91.28	0.69	91.31	0.00			94.02	0.00	96.12	0.00	96.64	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.90676189
94.03	0.11	94.19	0.00	91.30	0.03	91.31	0.00			94.03	0.02	96.12	0.00	97.26	0.62	/workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2016694001
94.14	0.11	94.39	0.20	91.39	0.09	91.35	0.04			94.10	0.07	96.30	0.18	97.31	0.05	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3430338207
94.25	0.10	94.41	0.02	91.45	0.06	91.67	0.32			94.13	0.03	96.49	0.18	97.32	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.525346106
94.34	0.10	94.41	0.00	91.52	0.07	91.67	0.00			94.15	0.02	96.49	0.00	97.83	0.51	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2192236991
94.44	0.09	94.54	0.14	91.64	0.12	91.86	0.19			94.27	0.12	96.49	0.00	97.83	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.542143566
94.53	0.09	94.56	0.01	91.64	0.01	92.38	0.52			94.27	0.00	96.49	0.00	97.83	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3546054073
94.61	0.09	94.56	0.00	91.65	0.01	92.86	0.48			94.27	0.00	96.49	0.00	97.86	0.04	/workspace/coverage/default/59.chip_sw_all_escalation_resets.651562924
94.70	0.08	94.56	0.00	91.88	0.23	92.89	0.03			94.52	0.25	96.49	0.00	97.86	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2744840218
94.76	0.06	94.56	0.00	91.88	0.00	93.26	0.37			94.52	0.00	96.49	0.00	97.86	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2130749197
94.82	0.06	94.61	0.05	92.01	0.13	93.37	0.11			94.58	0.06	96.49	0.00	97.86	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2612632536
94.87	0.05	94.61	0.00	92.01	0.00	93.70	0.32			94.58	0.00	96.49	0.00	97.86	0.00	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.685184058
94.92	0.05	94.61	0.00	92.30	0.30	93.70	0.00			94.58	0.00	96.49	0.00	97.87	0.01	/workspace/coverage/cover_reg_top/13.chip_tl_errors.1515472366
94.98	0.05	94.61	0.00	92.30	0.00	93.70	0.00			94.58	0.00	96.49	0.00	98.18	0.31	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.4272708840
95.02	0.05	94.64	0.03	92.31	0.01	93.75	0.06			94.59	0.01	96.67	0.18	98.19	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3735910028
95.07	0.05	94.69	0.05	92.45	0.14	93.75	0.00			94.67	0.08	96.67	0.00	98.19	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2057663039
95.12	0.04	94.70	0.01	92.46	0.01	93.75	0.00			94.69	0.02	96.86	0.18	98.23	0.04	/workspace/coverage/default/17.chip_sw_all_escalation_resets.440111504
95.16	0.04	94.71	0.01	92.47	0.01	93.76	0.01			94.70	0.01	97.04	0.18	98.27	0.05	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3800208937
95.20	0.04	94.78	0.07	92.47	0.00	93.93	0.17			94.71	0.01	97.04	0.00	98.27	0.00	/workspace/coverage/default/2.chip_tap_straps_rma.504702636
95.24	0.04	94.78	0.00	92.47	0.00	94.19	0.25			94.71	0.00	97.04	0.00	98.27	0.00	/workspace/coverage/default/1.chip_sw_kmac_entropy.2021110638
95.28	0.04	94.81	0.03	92.53	0.05	94.30	0.12			94.74	0.02	97.04	0.00	98.27	0.00	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.97109147
95.32	0.04	94.82	0.01	92.54	0.01	94.30	0.00			94.74	0.01	97.23	0.18	98.28	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.966245728
95.35	0.03	94.89	0.07	92.57	0.03	94.35	0.04			94.79	0.05	97.23	0.00	98.28	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.94768922
95.38	0.03	94.89	0.00	92.70	0.13	94.35	0.00			94.84	0.05	97.23	0.00	98.30	0.01	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2427595155
95.41	0.03	94.89	0.00	92.89	0.19	94.35	0.00			94.84	0.00	97.23	0.00	98.30	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1832797624
95.45	0.03	94.89	0.00	92.89	0.00	94.35	0.00			94.84	0.00	97.41	0.18	98.30	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1626004445
95.48	0.03	94.89	0.00	92.89	0.00	94.53	0.18			94.84	0.00	97.41	0.00	98.30	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3442805555
95.50	0.03	94.89	0.00	92.89	0.00	94.69	0.16			94.84	0.00	97.41	0.00	98.30	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1355308511
95.53	0.03	94.89	0.00	92.98	0.09	94.69	0.00			94.84	0.00	97.41	0.00	98.37	0.07	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.295303175
95.55	0.03	94.90	0.01	93.01	0.04	94.78	0.09			94.85	0.01	97.41	0.00	98.37	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.170255705
95.58	0.02	94.90	0.00	93.01	0.00	94.92	0.14			94.85	0.00	97.41	0.00	98.37	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.301282272
95.60	0.02	94.90	0.00	93.15	0.13	94.92	0.00			94.85	0.00	97.41	0.00	98.37	0.00	/workspace/coverage/cover_reg_top/6.chip_tl_errors.3251839764
95.62	0.02	94.90	0.00	93.15	0.00	94.92	0.00			94.85	0.00	97.41	0.00	98.50	0.13	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2913431365
95.64	0.02	94.92	0.01	93.20	0.05	94.94	0.02			94.88	0.03	97.41	0.00	98.50	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1877668633
95.66	0.02	94.92	0.00	93.22	0.02	95.03	0.08			94.88	0.00	97.41	0.00	98.50	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_aliasing.4006875769
95.67	0.02	94.92	0.00	93.27	0.05	95.03	0.00			94.88	0.00	97.41	0.00	98.54	0.05	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1665149541
95.69	0.02	94.92	0.00	93.36	0.09	95.03	0.00			94.88	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3416590971
95.70	0.01	94.92	0.00	93.38	0.02	95.04	0.02			94.88	0.00	97.41	0.00	98.59	0.05	/workspace/coverage/default/0.chip_sw_alert_test.363646497
95.72	0.01	94.94	0.03	93.41	0.04	95.07	0.03			94.88	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2379728319
95.73	0.01	94.94	0.00	93.49	0.08	95.07	0.00			94.88	0.00	97.41	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.2395445633
95.74	0.01	94.94	0.00	93.49	0.00	95.11	0.04			94.88	0.00	97.41	0.00	98.63	0.04	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.395239488
95.76	0.01	94.96	0.02	93.53	0.04	95.12	0.01			94.88	0.00	97.41	0.00	98.64	0.01	/workspace/coverage/cover_reg_top/18.chip_csr_rw.3541056722
95.77	0.01	94.96	0.00	93.53	0.00	95.19	0.07			94.88	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.872040083
95.78	0.01	95.00	0.04	93.55	0.02	95.20	0.01			94.89	0.01	97.41	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.770778795
95.79	0.01	95.00	0.00	93.55	0.00	95.27	0.07			94.89	0.00	97.41	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3362939790
95.80	0.01	95.00	0.00	93.61	0.06	95.27	0.00			94.89	0.00	97.41	0.00	98.65	0.01	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.665171715
95.82	0.01	95.04	0.04	93.63	0.02	95.27	0.00			94.90	0.01	97.41	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1231260477
95.82	0.01	95.04	0.00	93.63	0.01	95.32	0.05			94.90	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2146222200
95.83	0.01	95.04	0.00	93.67	0.04	95.32	0.00			94.92	0.02	97.41	0.00	98.65	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3301130160
95.84	0.01	95.04	0.00	93.72	0.05	95.32	0.00			94.92	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.186224397
95.85	0.01	95.04	0.00	93.72	0.00	95.36	0.05			94.92	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1222309511
95.86	0.01	95.04	0.00	93.73	0.01	95.39	0.03			94.92	0.00	97.41	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1048544557
95.86	0.01	95.04	0.00	93.76	0.03	95.39	0.00			94.92	0.01	97.41	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/41.xbar_stress_all.1622065103
95.87	0.01	95.04	0.00	93.76	0.00	95.39	0.00			94.92	0.00	97.41	0.00	98.68	0.04	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.206504554
95.87	0.01	95.04	0.00	93.76	0.00	95.39	0.00			94.92	0.00	97.41	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.904755302
95.88	0.01	95.04	0.00	93.76	0.00	95.42	0.03			94.92	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.164753299
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96.10	0.01	95.07	0.00	94.09	0.00	95.59	0.00			94.92	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/74.chip_sw_all_escalation_resets.2758209430
96.10	0.01	95.07	0.00	94.09	0.00	95.59	0.00			94.92	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2784351340
96.10	0.01	95.07	0.00	94.09	0.00	95.59	0.00			94.92	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.2227226769
96.10	0.01	95.07	0.00	94.09	0.00	95.59	0.00			94.92	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318804978
96.11	0.01	95.07	0.00	94.09	0.00	95.59	0.00			94.92	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2749597274
96.11	0.01	95.07	0.00	94.09	0.00	95.59	0.00			94.92	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2154791193
96.11	0.01	95.07	0.00	94.09	0.00	95.59	0.00			94.92	0.00	97.41	0.00	99.57	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.3163355532
96.11	0.01	95.07	0.00	94.09	0.00	95.59	0.00			94.92	0.00	97.41	0.00	99.58	0.01	/workspace/coverage/default/96.chip_sw_all_escalation_resets.4151250681
96.11	0.01	95.07	0.00	94.10	0.01	95.59	0.00			94.92	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.910977269
96.11	0.01	95.07	0.00	94.11	0.01	95.59	0.00			94.92	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3817660430
96.12	0.01	95.07	0.00	94.12	0.01	95.59	0.00			94.92	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_gpio.1938861346
96.12	0.01	95.08	0.01	94.12	0.00	95.60	0.01			94.92	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.1894387493
96.12	0.01	95.08	0.01	94.12	0.00	95.61	0.01			94.92	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1545564681
96.12	0.01	95.08	0.00	94.13	0.01	95.61	0.01			94.92	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2327044962
96.12	0.01	95.08	0.00	94.13	0.00	95.62	0.01			94.92	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.71052024
96.13	0.01	95.08	0.00	94.13	0.00	95.63	0.01			94.92	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2215924623
96.13	0.01	95.08	0.00	94.13	0.00	95.63	0.00			94.93	0.01	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2231017530
96.13	0.01	95.08	0.00	94.13	0.00	95.63	0.00			94.94	0.01	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3710966304
96.13	0.01	95.08	0.00	94.13	0.01	95.63	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1339522020
96.13	0.01	95.08	0.00	94.14	0.01	95.63	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_aon_timer_irq.3857997498
96.13	0.01	95.08	0.00	94.15	0.01	95.63	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1519088400
96.13	0.01	95.09	0.01	94.15	0.00	95.63	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4184200808
96.13	0.01	95.09	0.01	94.15	0.00	95.63	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1982527996
96.13	0.01	95.09	0.00	94.15	0.00	95.64	0.01			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1197895894
96.14	0.01	95.09	0.00	94.15	0.00	95.65	0.01			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1266589351
96.14	0.01	95.09	0.00	94.15	0.00	95.65	0.01			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2947506723
96.14	0.01	95.09	0.00	94.15	0.01	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/10.xbar_same_source.3659453131
96.14	0.01	95.09	0.00	94.16	0.01	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3583311256
96.14	0.01	95.09	0.00	94.16	0.01	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.469658276
96.14	0.01	95.09	0.00	94.16	0.01	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.606952544
96.14	0.01	95.09	0.00	94.17	0.01	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.3033122195
96.14	0.01	95.09	0.00	94.17	0.01	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.3393277087
96.14	0.01	95.09	0.00	94.17	0.01	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.2071402270
96.14	0.01	95.09	0.00	94.18	0.01	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.94032937
96.14	0.01	95.09	0.00	94.18	0.01	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1543847767
96.14	0.01	95.10	0.01	94.18	0.00	95.65	0.00			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.1499529169
96.14	0.01	95.10	0.00	94.18	0.00	95.65	0.01			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3506827966
96.14	0.01	95.10	0.00	94.18	0.00	95.65	0.01			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.22528033
96.14	0.01	95.10	0.00	94.18	0.00	95.66	0.01			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2644072570
96.14	0.01	95.10	0.00	94.18	0.00	95.66	0.01			94.94	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_kmac_idle.2517227242

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.4246914584
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1903940245
/workspace/coverage/cover_reg_top/0.chip_csr_rw.3219764471
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2779778395
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3302355825
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1824876490
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3440522377
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3206702290
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3338505460
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3553515110
/workspace/coverage/cover_reg_top/0.xbar_error_random.3990786117
/workspace/coverage/cover_reg_top/0.xbar_random.2132967932
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2222278094
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.97762265
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1396994439
/workspace/coverage/cover_reg_top/0.xbar_same_source.814112449
/workspace/coverage/cover_reg_top/0.xbar_smoke.3619131414
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.132669003
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2517340874
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.824736003
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3711763014
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3624289579
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.23790638
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1606713484
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.262960050
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3189829756
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2689438314
/workspace/coverage/cover_reg_top/1.chip_csr_rw.361474281
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.802303510
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1689811272
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3371463433
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1471307001
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3890074197
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2367555550
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4064714829
/workspace/coverage/cover_reg_top/1.xbar_error_random.205093232
/workspace/coverage/cover_reg_top/1.xbar_random.3646889567
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3472285840
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3696632810
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2576695097
/workspace/coverage/cover_reg_top/1.xbar_same_source.4190923547
/workspace/coverage/cover_reg_top/1.xbar_smoke.3478526831
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.660546857
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3401779055
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.577431956
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1405059320
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3006180979
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.754037415
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3382256881
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3098770866
/workspace/coverage/cover_reg_top/10.chip_csr_rw.4021440436
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2252446191
/workspace/coverage/cover_reg_top/10.chip_tl_errors.346013639
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.4103558310
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2931832195
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2956063908
/workspace/coverage/cover_reg_top/10.xbar_error_random.919560133
/workspace/coverage/cover_reg_top/10.xbar_random.704177762
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.507972930
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.927328504
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.405230572
/workspace/coverage/cover_reg_top/10.xbar_smoke.2111654164
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1004094352
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3413496933
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2086595730
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2686972253
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2289490916
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2049257059
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.54730629
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1286034274
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.625285552
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3658894060
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2880160562
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3120077237
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.362704114
/workspace/coverage/cover_reg_top/11.xbar_error_random.879718092
/workspace/coverage/cover_reg_top/11.xbar_random.247863343
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3144725472
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2751323823
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1575095596
/workspace/coverage/cover_reg_top/11.xbar_same_source.1646297918
/workspace/coverage/cover_reg_top/11.xbar_smoke.933768972
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2475996383
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1028133622
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.475798977
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2416478901
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.4272400065
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1476720698
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1766230243
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3759628150
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2814622238
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3974651146
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2349812486
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3635858208
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.200667889
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3844222809
/workspace/coverage/cover_reg_top/12.xbar_error_random.3827131224
/workspace/coverage/cover_reg_top/12.xbar_random.1043927187
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3922139132
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3156659510
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3881818335
/workspace/coverage/cover_reg_top/12.xbar_same_source.3162167260
/workspace/coverage/cover_reg_top/12.xbar_smoke.3597621197
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2359672542
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.409541849
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3859536679
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2133813148
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2363445480
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1233730047
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.563881536
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1846696292
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1581422135
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1761021398
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2864969735
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.828984620
/workspace/coverage/cover_reg_top/13.xbar_error_random.3675313074
/workspace/coverage/cover_reg_top/13.xbar_random.243871167
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2071863639
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1881245868
/workspace/coverage/cover_reg_top/13.xbar_same_source.1999493120
/workspace/coverage/cover_reg_top/13.xbar_smoke.4077164056
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2057239017
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.617739587
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1601034150
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3129914370
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3619446093
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2987231170
/workspace/coverage/cover_reg_top/14.chip_csr_rw.1243769314
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3449140672
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1021619852
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.660287261
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1901891945
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2289912371
/workspace/coverage/cover_reg_top/14.xbar_error_random.3637535590
/workspace/coverage/cover_reg_top/14.xbar_random.3222676229
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.446659106
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.374130091
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2887355993
/workspace/coverage/cover_reg_top/14.xbar_same_source.960977851
/workspace/coverage/cover_reg_top/14.xbar_smoke.4180102879
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1576252078
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3775307231
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1747257031
/workspace/coverage/cover_reg_top/14.xbar_stress_all.1680856240
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1100766155
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.4090597319
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1759769749
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3287035829
/workspace/coverage/cover_reg_top/15.chip_csr_rw.2772345008
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.1227455697
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/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1532255260
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3872290192
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1702468482
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.4270192765
/workspace/coverage/default/4.chip_tap_straps_dev.2630000303
/workspace/coverage/default/4.chip_tap_straps_prod.1370933037
/workspace/coverage/default/4.chip_tap_straps_rma.4146905277
/workspace/coverage/default/4.chip_tap_straps_testunlock0.512595805
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1438545645
/workspace/coverage/default/40.chip_sw_all_escalation_resets.782719469
/workspace/coverage/default/41.chip_sw_all_escalation_resets.144594893
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.441872312
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2308633385
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2739518150
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4256198935
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1900177179
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.47833758
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3119785242
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3094421724
/workspace/coverage/default/47.chip_sw_all_escalation_resets.4038977914
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1231863531
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3314246925
/workspace/coverage/default/49.chip_sw_all_escalation_resets.281871420
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2178008250
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3544907337
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1299468360
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1519015147
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1741376621
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.349143126
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1311206571
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.747046080
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3262948323
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3664096907
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2237124931
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3987534820
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3681040210
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1452839034
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2433155154
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3045151680
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.362323489
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3726550009
/workspace/coverage/default/6.chip_sw_all_escalation_resets.652724582
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2724270054
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3059065534
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1157189205
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1409806815
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2087873245
/workspace/coverage/default/62.chip_sw_all_escalation_resets.4102035869
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.190608469
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2480376300
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871610735
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1556924665
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2418769060
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2555901422
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3453242157
/workspace/coverage/default/66.chip_sw_all_escalation_resets.645355843
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.449887988
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2646985403
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.802059278
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3489152483
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1159027838
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878075635
/workspace/coverage/default/7.chip_sw_all_escalation_resets.153888602
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.971111409
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558828425
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1705765269
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1227035188
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1146540197
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2592650728
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1402991880
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1726703474
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3976200881
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1557815001
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1707522211
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1676728012
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2437341646
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1023763362
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188998302
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.806534700
/workspace/coverage/default/79.chip_sw_all_escalation_resets.4211309386
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2738957918
/workspace/coverage/default/8.chip_sw_all_escalation_resets.596099548
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2438490013
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3687280994
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1939349934
/workspace/coverage/default/80.chip_sw_all_escalation_resets.110836542
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.22788456
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3047035891
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.96805501
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2489418142
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2704479189
/workspace/coverage/default/83.chip_sw_all_escalation_resets.806962282
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2923870744
/workspace/coverage/default/85.chip_sw_all_escalation_resets.4031136781
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1406495661
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1689272897
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4209114368
/workspace/coverage/default/87.chip_sw_all_escalation_resets.355824719
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3750434503
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2501159619
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3273410142
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2908342187
/workspace/coverage/default/9.chip_sw_all_escalation_resets.52592101
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3065105605
/workspace/coverage/default/91.chip_sw_all_escalation_resets.4235061753
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1852523926
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3445321860
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3101903985
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2014906671
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1515470899
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2047613303
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2955239855
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4095542190
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.491003937
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.117248745
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.27442329
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4122399716
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2155929479

---

Total test records in report: 2838

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.77961675			Mar 26 04:02:24 PM PDT 24	Mar 26 04:08:51 PM PDT 24	3808490960 ps
T2	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1761504413			Mar 26 03:51:42 PM PDT 24	Mar 26 04:22:07 PM PDT 24	13341065960 ps
T3	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1715194490			Mar 26 04:10:59 PM PDT 24	Mar 26 04:18:32 PM PDT 24	3720823900 ps
T31	/workspace/coverage/default/20.chip_sw_all_escalation_resets.4183116294			Mar 26 04:08:16 PM PDT 24	Mar 26 04:17:45 PM PDT 24	4562221438 ps
T85	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1048544557			Mar 26 03:53:09 PM PDT 24	Mar 26 04:06:33 PM PDT 24	4647128041 ps
T32	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1894635669			Mar 26 03:52:39 PM PDT 24	Mar 26 03:57:09 PM PDT 24	4209905864 ps
T13	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.97109147			Mar 26 04:10:01 PM PDT 24	Mar 26 05:00:05 PM PDT 24	22959795920 ps
T86	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.542143566			Mar 26 04:00:50 PM PDT 24	Mar 26 04:06:11 PM PDT 24	2679459542 ps
T87	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1439526696			Mar 26 04:04:04 PM PDT 24	Mar 26 04:09:51 PM PDT 24	3129118092 ps
T59	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3307002595			Mar 26 04:11:11 PM PDT 24	Mar 26 04:19:31 PM PDT 24	3391578544 ps
T125	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.4065328743			Mar 26 03:45:43 PM PDT 24	Mar 26 04:43:31 PM PDT 24	17277022228 ps
T203	/workspace/coverage/default/4.chip_sw_uart_tx_rx.1543543443			Mar 26 04:06:59 PM PDT 24	Mar 26 04:21:55 PM PDT 24	5896635344 ps
T119	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.395239488			Mar 26 03:45:22 PM PDT 24	Mar 26 03:52:17 PM PDT 24	4958911496 ps
T827	/workspace/coverage/default/0.chip_sw_example_flash.3028920912			Mar 26 03:47:08 PM PDT 24	Mar 26 03:51:49 PM PDT 24	2843958370 ps
T60	/workspace/coverage/default/66.chip_sw_all_escalation_resets.645355843			Mar 26 04:11:39 PM PDT 24	Mar 26 04:22:39 PM PDT 24	4409287890 ps
T115	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2732444259			Mar 26 03:48:08 PM PDT 24	Mar 26 04:07:03 PM PDT 24	5269271779 ps
T110	/workspace/coverage/default/2.chip_sw_power_sleep_load.2749383462			Mar 26 04:04:36 PM PDT 24	Mar 26 04:09:08 PM PDT 24	4462166120 ps
T176	/workspace/coverage/default/13.chip_sw_all_escalation_resets.525346106			Mar 26 04:10:06 PM PDT 24	Mar 26 04:22:11 PM PDT 24	4602636690 ps
T114	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3503198701			Mar 26 04:02:40 PM PDT 24	Mar 26 05:04:50 PM PDT 24	18988463107 ps
T372	/workspace/coverage/default/2.chip_sw_aes_idle.4171623517			Mar 26 04:00:54 PM PDT 24	Mar 26 04:05:39 PM PDT 24	3315874120 ps
T373	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1065863429			Mar 26 04:02:58 PM PDT 24	Mar 26 04:14:04 PM PDT 24	4409538624 ps
T122	/workspace/coverage/default/0.chip_sw_edn_kat.3926328614			Mar 26 03:46:47 PM PDT 24	Mar 26 03:58:47 PM PDT 24	3563082556 ps
T168	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3262948323			Mar 26 04:10:39 PM PDT 24	Mar 26 04:20:56 PM PDT 24	5360538628 ps
T120	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3612545168			Mar 26 04:06:27 PM PDT 24	Mar 26 04:13:00 PM PDT 24	6661874912 ps
T69	/workspace/coverage/default/1.chip_tap_straps_prod.2404594655			Mar 26 03:48:31 PM PDT 24	Mar 26 04:22:13 PM PDT 24	16342356577 ps
T14	/workspace/coverage/default/1.chip_sw_gpio.1682550960			Mar 26 03:48:29 PM PDT 24	Mar 26 03:55:14 PM PDT 24	3550997129 ps
T121	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.559606776			Mar 26 03:59:15 PM PDT 24	Mar 26 04:28:28 PM PDT 24	14122448252 ps
T622	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1406495661			Mar 26 04:13:35 PM PDT 24	Mar 26 04:20:47 PM PDT 24	3707435718 ps
T177	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.47322371			Mar 26 04:05:47 PM PDT 24	Mar 26 04:14:56 PM PDT 24	7684046960 ps
T123	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2078973168			Mar 26 04:00:29 PM PDT 24	Mar 26 04:25:16 PM PDT 24	6753045992 ps
T4	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2139100924			Mar 26 03:46:46 PM PDT 24	Mar 26 05:07:26 PM PDT 24	45490388298 ps
T206	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2139622220			Mar 26 03:49:12 PM PDT 24	Mar 26 03:51:55 PM PDT 24	2184588530 ps
T5	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3188680508			Mar 26 04:05:35 PM PDT 24	Mar 26 04:12:51 PM PDT 24	4544657633 ps
T298	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2739518150			Mar 26 04:09:25 PM PDT 24	Mar 26 04:15:37 PM PDT 24	3595242044 ps
T235	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.364864991			Mar 26 03:47:19 PM PDT 24	Mar 26 03:57:00 PM PDT 24	5717683412 ps
T659	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3568887045			Mar 26 04:08:26 PM PDT 24	Mar 26 04:15:18 PM PDT 24	4256707324 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4066549508			Mar 26 04:04:12 PM PDT 24	Mar 26 04:34:34 PM PDT 24	21675183080 ps
T6	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1299468360			Mar 26 04:08:00 PM PDT 24	Mar 26 04:14:52 PM PDT 24	4950183180 ps
T102	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1104256479			Mar 26 04:07:50 PM PDT 24	Mar 26 04:15:21 PM PDT 24	3524059104 ps
T103	/workspace/coverage/default/0.chip_sw_aon_timer_irq.302271509			Mar 26 03:48:37 PM PDT 24	Mar 26 03:55:58 PM PDT 24	3830056832 ps
T104	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188998302			Mar 26 04:11:56 PM PDT 24	Mar 26 04:19:10 PM PDT 24	3958991996 ps
T105	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2359386867			Mar 26 03:47:02 PM PDT 24	Mar 26 03:56:15 PM PDT 24	6494891220 ps
T106	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2908342187			Mar 26 04:07:46 PM PDT 24	Mar 26 04:14:58 PM PDT 24	3887236992 ps
T107	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.94768922			Mar 26 04:02:09 PM PDT 24	Mar 26 04:19:09 PM PDT 24	8442879682 ps
T108	/workspace/coverage/default/0.chip_sw_aes_enc.3608805566			Mar 26 03:48:47 PM PDT 24	Mar 26 03:53:06 PM PDT 24	3105490780 ps
T109	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3403696453			Mar 26 03:46:16 PM PDT 24	Mar 26 03:56:18 PM PDT 24	5018189081 ps
T280	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.94032937			Mar 26 03:46:55 PM PDT 24	Mar 26 04:01:31 PM PDT 24	5125936612 ps
T241	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2694323536			Mar 26 03:52:53 PM PDT 24	Mar 26 03:57:41 PM PDT 24	2821671552 ps
T145	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2617381312			Mar 26 04:01:27 PM PDT 24	Mar 26 04:24:24 PM PDT 24	5771068036 ps
T281	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2749597274			Mar 26 04:16:48 PM PDT 24	Mar 26 04:22:40 PM PDT 24	3550737268 ps
T282	/workspace/coverage/default/91.chip_sw_all_escalation_resets.4235061753			Mar 26 04:15:16 PM PDT 24	Mar 26 04:27:37 PM PDT 24	5362199592 ps
T15	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4243506995			Mar 26 04:07:44 PM PDT 24	Mar 26 04:24:06 PM PDT 24	5925451000 ps
T42	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2736311086			Mar 26 04:09:56 PM PDT 24	Mar 26 04:35:54 PM PDT 24	7043649472 ps
T39	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3564284800			Mar 26 03:57:34 PM PDT 24	Mar 26 04:53:48 PM PDT 24	11974839960 ps
T166	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1306536602			Mar 26 03:53:25 PM PDT 24	Mar 26 03:59:59 PM PDT 24	4123301490 ps
T354	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2067581324			Mar 26 03:49:01 PM PDT 24	Mar 26 03:52:39 PM PDT 24	2720105388 ps
T233	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3735910028			Mar 26 04:14:22 PM PDT 24	Mar 26 04:25:56 PM PDT 24	5324040396 ps
T43	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1061120496			Mar 26 03:57:42 PM PDT 24	Mar 26 04:41:03 PM PDT 24	8905986906 ps
T162	/workspace/coverage/default/2.chip_sival_flash_info_access.750728371			Mar 26 03:55:25 PM PDT 24	Mar 26 03:59:45 PM PDT 24	2900244346 ps
T124	/workspace/coverage/default/0.chip_sw_edn_boot_mode.22528033			Mar 26 03:48:02 PM PDT 24	Mar 26 03:56:18 PM PDT 24	2889773980 ps
T220	/workspace/coverage/default/1.rom_e2e_asm_init_prod.327097237			Mar 26 03:56:46 PM PDT 24	Mar 26 04:32:59 PM PDT 24	8473052198 ps
T257	/workspace/coverage/default/0.chip_sw_hmac_enc.401940663			Mar 26 03:47:49 PM PDT 24	Mar 26 03:52:12 PM PDT 24	2926568490 ps
T40	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.4052953408			Mar 26 03:55:58 PM PDT 24	Mar 26 04:33:31 PM PDT 24	8610352526 ps
T258	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.794402537			Mar 26 04:02:47 PM PDT 24	Mar 26 04:27:43 PM PDT 24	11263950035 ps
T259	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3687358837			Mar 26 04:06:57 PM PDT 24	Mar 26 04:14:13 PM PDT 24	4139837160 ps
T167	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.374020249			Mar 26 03:54:04 PM PDT 24	Mar 26 04:00:54 PM PDT 24	3825283856 ps
T357	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.96805501			Mar 26 04:16:24 PM PDT 24	Mar 26 04:24:15 PM PDT 24	3445160258 ps
T198	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1692972471			Mar 26 03:49:21 PM PDT 24	Mar 26 03:56:48 PM PDT 24	3663503324 ps
T328	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3404799551			Mar 26 03:47:37 PM PDT 24	Mar 26 03:59:36 PM PDT 24	4919355672 ps
T189	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.685184058			Mar 26 04:07:58 PM PDT 24	Mar 26 04:25:19 PM PDT 24	11234324109 ps
T64	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.935371781			Mar 26 04:07:24 PM PDT 24	Mar 26 04:15:03 PM PDT 24	3839952874 ps
T264	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2206529157			Mar 26 03:47:21 PM PDT 24	Mar 26 03:55:16 PM PDT 24	9673298474 ps
T157	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.20934794			Mar 26 03:46:02 PM PDT 24	Mar 26 05:09:37 PM PDT 24	49802754625 ps
T148	/workspace/coverage/default/1.chip_plic_all_irqs_10.4021622637			Mar 26 03:56:39 PM PDT 24	Mar 26 04:06:00 PM PDT 24	3663704136 ps
T240	/workspace/coverage/default/0.chip_sw_plic_sw_irq.394722180			Mar 26 03:47:25 PM PDT 24	Mar 26 03:52:47 PM PDT 24	2930269064 ps
T828	/workspace/coverage/default/2.chip_sw_aon_timer_irq.659358554			Mar 26 04:00:56 PM PDT 24	Mar 26 04:06:29 PM PDT 24	4057703160 ps
T829	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1699738619			Mar 26 03:51:47 PM PDT 24	Mar 26 04:38:44 PM PDT 24	36994896300 ps
T127	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3190334515			Mar 26 03:45:55 PM PDT 24	Mar 26 03:53:12 PM PDT 24	6197844304 ps
T207	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.802059278			Mar 26 04:11:12 PM PDT 24	Mar 26 04:19:49 PM PDT 24	4085651528 ps
T178	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2544578125			Mar 26 03:49:06 PM PDT 24	Mar 26 03:57:36 PM PDT 24	4106958784 ps
T65	/workspace/coverage/default/0.chip_jtag_csr_rw.579379369			Mar 26 03:36:46 PM PDT 24	Mar 26 03:59:30 PM PDT 24	12566723332 ps
T299	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1159027838			Mar 26 04:12:14 PM PDT 24	Mar 26 04:19:35 PM PDT 24	4164025050 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_pullup.2932196154			Mar 26 03:44:38 PM PDT 24	Mar 26 03:50:29 PM PDT 24	3573137140 ps
T658	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.47833758			Mar 26 04:10:22 PM PDT 24	Mar 26 04:16:44 PM PDT 24	3955211736 ps
T208	/workspace/coverage/default/55.chip_sw_all_escalation_resets.3681040210			Mar 26 04:11:02 PM PDT 24	Mar 26 04:23:40 PM PDT 24	5887836538 ps
T830	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3690804161			Mar 26 03:59:15 PM PDT 24	Mar 26 04:10:03 PM PDT 24	4025786154 ps
T655	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2095781879			Mar 26 04:10:57 PM PDT 24	Mar 26 04:18:18 PM PDT 24	3613647544 ps
T248	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342650194			Mar 26 04:10:45 PM PDT 24	Mar 26 04:17:19 PM PDT 24	3789513116 ps
T70	/workspace/coverage/default/0.chip_tap_straps_prod.1443718650			Mar 26 03:47:13 PM PDT 24	Mar 26 03:57:47 PM PDT 24	6817906806 ps
T505	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4062546557			Mar 26 04:02:38 PM PDT 24	Mar 26 04:17:33 PM PDT 24	5215955016 ps
T250	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1908628704			Mar 26 04:07:29 PM PDT 24	Mar 26 04:10:17 PM PDT 24	3110269278 ps
T194	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3145780347			Mar 26 03:45:50 PM PDT 24	Mar 26 03:59:29 PM PDT 24	4186505004 ps
T329	/workspace/coverage/default/29.chip_sw_all_escalation_resets.303066055			Mar 26 04:08:45 PM PDT 24	Mar 26 04:19:33 PM PDT 24	5123355054 ps
T300	/workspace/coverage/default/0.chip_plic_all_irqs_0.2495226587			Mar 26 03:48:37 PM PDT 24	Mar 26 04:11:29 PM PDT 24	6642203820 ps
T79	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4131663279			Mar 26 04:09:16 PM PDT 24	Mar 26 04:15:52 PM PDT 24	3514544998 ps
T93	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.667878773			Mar 26 03:50:44 PM PDT 24	Mar 26 04:02:47 PM PDT 24	4908260920 ps
T94	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1711392903			Mar 26 04:00:18 PM PDT 24	Mar 26 04:09:52 PM PDT 24	6740053992 ps
T95	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1094544818			Mar 26 03:44:43 PM PDT 24	Mar 26 03:53:49 PM PDT 24	4780786472 ps
T96	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2178474779			Mar 26 03:57:36 PM PDT 24	Mar 26 04:13:18 PM PDT 24	5886284160 ps
T97	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3047035891			Mar 26 04:14:45 PM PDT 24	Mar 26 04:24:08 PM PDT 24	5393923576 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.675018845			Mar 26 03:50:43 PM PDT 24	Mar 26 04:24:44 PM PDT 24	24342695816 ps
T98	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1023763362			Mar 26 04:11:40 PM PDT 24	Mar 26 04:18:00 PM PDT 24	4513305108 ps
T99	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3362939790			Mar 26 03:52:31 PM PDT 24	Mar 26 04:05:49 PM PDT 24	3745422400 ps
T100	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3224031734			Mar 26 03:50:09 PM PDT 24	Mar 26 04:05:58 PM PDT 24	5568958438 ps
T358	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3223690101			Mar 26 03:52:27 PM PDT 24	Mar 26 04:47:51 PM PDT 24	11624469616 ps
T199	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4184200808			Mar 26 03:45:14 PM PDT 24	Mar 26 03:57:53 PM PDT 24	5221517900 ps
T632	/workspace/coverage/default/87.chip_sw_all_escalation_resets.355824719			Mar 26 04:12:34 PM PDT 24	Mar 26 04:23:42 PM PDT 24	5280783348 ps
T320	/workspace/coverage/default/2.chip_sw_pattgen_ios.1804296661			Mar 26 03:55:29 PM PDT 24	Mar 26 03:59:02 PM PDT 24	2651623432 ps
T660	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2178008250			Mar 26 04:09:14 PM PDT 24	Mar 26 04:17:22 PM PDT 24	3424203200 ps
T41	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3210447290			Mar 26 03:56:11 PM PDT 24	Mar 26 04:27:58 PM PDT 24	9232930372 ps
T179	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3430338207			Mar 26 03:47:48 PM PDT 24	Mar 26 03:56:10 PM PDT 24	4868180104 ps
T831	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1444002319			Mar 26 03:49:01 PM PDT 24	Mar 26 04:02:35 PM PDT 24	7013205026 ps
T417	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3987534820			Mar 26 04:11:42 PM PDT 24	Mar 26 04:17:32 PM PDT 24	4026594498 ps
T80	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2923870744			Mar 26 04:12:14 PM PDT 24	Mar 26 04:22:36 PM PDT 24	5029347200 ps
T330	/workspace/coverage/default/27.chip_sw_all_escalation_resets.1260635626			Mar 26 04:11:28 PM PDT 24	Mar 26 04:23:40 PM PDT 24	5440241500 ps
T116	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2656577027			Mar 26 04:02:16 PM PDT 24	Mar 26 04:11:47 PM PDT 24	5292262367 ps
T633	/workspace/coverage/default/15.chip_sw_all_escalation_resets.2277593704			Mar 26 04:08:20 PM PDT 24	Mar 26 04:17:49 PM PDT 24	5297619712 ps
T245	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.756503169			Mar 26 03:53:46 PM PDT 24	Mar 26 04:48:22 PM PDT 24	14026605400 ps
T365	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2980122674			Mar 26 04:08:38 PM PDT 24	Mar 26 04:17:58 PM PDT 24	4371761504 ps
T66	/workspace/coverage/default/0.chip_tap_straps_testunlock0.1563108761			Mar 26 03:47:43 PM PDT 24	Mar 26 03:50:11 PM PDT 24	2314409382 ps
T832	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2256507801			Mar 26 04:06:43 PM PDT 24	Mar 26 04:16:12 PM PDT 24	5465633013 ps
T419	/workspace/coverage/default/0.chip_sw_kmac_idle.2517227242			Mar 26 03:47:48 PM PDT 24	Mar 26 03:52:07 PM PDT 24	3483338804 ps
T117	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3886054917			Mar 26 03:50:21 PM PDT 24	Mar 26 03:58:27 PM PDT 24	4709986702 ps
T408	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1227035188			Mar 26 04:12:26 PM PDT 24	Mar 26 04:19:18 PM PDT 24	4091870272 ps
T205	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3051299018			Mar 26 03:49:51 PM PDT 24	Mar 26 03:56:32 PM PDT 24	5771937562 ps
T689	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.362323489			Mar 26 04:11:12 PM PDT 24	Mar 26 04:18:10 PM PDT 24	3430548476 ps
T335	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3929894047			Mar 26 03:54:12 PM PDT 24	Mar 26 03:57:44 PM PDT 24	2610347549 ps
T118	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3538131409			Mar 26 03:49:21 PM PDT 24	Mar 26 03:59:10 PM PDT 24	4522478582 ps
T833	/workspace/coverage/default/0.chip_sw_uart_smoketest.689197124			Mar 26 03:46:03 PM PDT 24	Mar 26 03:50:06 PM PDT 24	2901518042 ps
T621	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.22483199			Mar 26 03:53:12 PM PDT 24	Mar 26 04:30:32 PM PDT 24	8991790704 ps
T75	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2572488203			Mar 26 03:52:07 PM PDT 24	Mar 26 04:00:18 PM PDT 24	4349635340 ps
T159	/workspace/coverage/default/58.chip_sw_all_escalation_resets.3726550009			Mar 26 04:11:15 PM PDT 24	Mar 26 04:20:45 PM PDT 24	5726669374 ps
T158	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2156298741			Mar 26 03:50:31 PM PDT 24	Mar 26 04:08:27 PM PDT 24	9361672210 ps
T246	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3506827966			Mar 26 03:46:05 PM PDT 24	Mar 26 04:00:28 PM PDT 24	3963060014 ps
T341	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2318649633			Mar 26 03:54:02 PM PDT 24	Mar 26 04:31:49 PM PDT 24	24995222296 ps
T418	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1157189205			Mar 26 04:11:29 PM PDT 24	Mar 26 04:16:49 PM PDT 24	3284712902 ps
T303	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.4270192765			Mar 26 04:13:07 PM PDT 24	Mar 26 04:27:56 PM PDT 24	5478646190 ps
T834	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2068227767			Mar 26 03:49:59 PM PDT 24	Mar 26 03:54:05 PM PDT 24	3235807045 ps
T835	/workspace/coverage/default/2.chip_sw_kmac_smoketest.3536276942			Mar 26 04:05:17 PM PDT 24	Mar 26 04:11:43 PM PDT 24	3112743702 ps
T210	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.347053605			Mar 26 03:48:46 PM PDT 24	Mar 26 03:59:45 PM PDT 24	5263024432 ps
T275	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2997157459			Mar 26 04:01:28 PM PDT 24	Mar 26 04:12:04 PM PDT 24	5099309656 ps
T58	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.554061433			Mar 26 04:06:12 PM PDT 24	Mar 26 04:13:36 PM PDT 24	5958719836 ps
T212	/workspace/coverage/default/47.chip_sw_all_escalation_resets.4038977914			Mar 26 04:09:43 PM PDT 24	Mar 26 04:21:20 PM PDT 24	4766841740 ps
T200	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.439156878			Mar 26 03:56:06 PM PDT 24	Mar 26 04:16:06 PM PDT 24	9090984504 ps
T10	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3147269284			Mar 26 03:48:26 PM PDT 24	Mar 26 03:59:08 PM PDT 24	4867956829 ps
T635	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.230503636			Mar 26 04:01:33 PM PDT 24	Mar 26 04:48:17 PM PDT 24	12415948040 ps
T247	/workspace/coverage/default/79.chip_sw_all_escalation_resets.4211309386			Mar 26 04:14:46 PM PDT 24	Mar 26 04:25:48 PM PDT 24	4062498760 ps
T111	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3546054073			Mar 26 03:54:26 PM PDT 24	Mar 26 05:16:07 PM PDT 24	29961232953 ps
T231	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2992252000			Mar 26 03:46:54 PM PDT 24	Mar 26 04:06:24 PM PDT 24	8645156764 ps
T152	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1519088400			Mar 26 03:53:53 PM PDT 24	Mar 26 04:20:57 PM PDT 24	13424696484 ps
T836	/workspace/coverage/default/2.chip_sw_otbn_randomness.2728724787			Mar 26 04:02:07 PM PDT 24	Mar 26 04:19:42 PM PDT 24	5890036198 ps
T662	/workspace/coverage/default/9.chip_sw_all_escalation_resets.52592101			Mar 26 04:07:17 PM PDT 24	Mar 26 04:21:04 PM PDT 24	5780988084 ps
T837	/workspace/coverage/default/2.rom_e2e_asm_init_rma.2595947082			Mar 26 04:11:35 PM PDT 24	Mar 26 04:42:30 PM PDT 24	8228997349 ps
T356	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.117298739			Mar 26 04:08:50 PM PDT 24	Mar 26 04:15:17 PM PDT 24	3510145256 ps
T359	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2327044962			Mar 26 03:57:53 PM PDT 24	Mar 26 04:44:45 PM PDT 24	9866787282 ps
T677	/workspace/coverage/default/64.chip_sw_all_escalation_resets.1556924665			Mar 26 04:10:51 PM PDT 24	Mar 26 04:20:06 PM PDT 24	4482381706 ps
T265	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3882378901			Mar 26 03:51:21 PM PDT 24	Mar 26 03:58:40 PM PDT 24	10086174601 ps
T180	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1655075345			Mar 26 03:48:37 PM PDT 24	Mar 26 03:54:48 PM PDT 24	3326910728 ps
T211	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3054481012			Mar 26 04:04:17 PM PDT 24	Mar 26 04:13:57 PM PDT 24	4088583396 ps
T292	/workspace/coverage/default/92.chip_sw_all_escalation_resets.3163355532			Mar 26 04:14:16 PM PDT 24	Mar 26 04:25:50 PM PDT 24	5558105408 ps
T293	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.714148264			Mar 26 03:59:24 PM PDT 24	Mar 26 04:38:51 PM PDT 24	19944015557 ps
T232	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.913112310			Mar 26 03:47:10 PM PDT 24	Mar 26 04:10:51 PM PDT 24	6740103798 ps
T242	/workspace/coverage/default/1.chip_sw_rv_timer_irq.1184708396			Mar 26 03:49:12 PM PDT 24	Mar 26 03:52:54 PM PDT 24	2428670970 ps
T294	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3840353802			Mar 26 03:47:29 PM PDT 24	Mar 26 03:54:43 PM PDT 24	6943789160 ps
T191	/workspace/coverage/default/1.chip_sw_power_idle_load.3955143923			Mar 26 03:50:24 PM PDT 24	Mar 26 04:01:23 PM PDT 24	4233622760 ps
T295	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2761561414			Mar 26 04:06:52 PM PDT 24	Mar 26 04:16:49 PM PDT 24	4967117940 ps
T296	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2264588952			Mar 26 04:04:08 PM PDT 24	Mar 26 04:13:57 PM PDT 24	6242855370 ps
T838	/workspace/coverage/default/2.chip_sw_example_rom.2211407208			Mar 26 03:54:23 PM PDT 24	Mar 26 03:56:13 PM PDT 24	1898349646 ps
T342	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1459459295			Mar 26 03:45:53 PM PDT 24	Mar 26 03:51:52 PM PDT 24	3884690770 ps
T76	/workspace/coverage/default/0.rom_raw_unlock.3563607347			Mar 26 03:47:13 PM PDT 24	Mar 26 04:26:03 PM PDT 24	16924966948 ps
T234	/workspace/coverage/default/45.chip_sw_all_escalation_resets.4060250704			Mar 26 04:10:00 PM PDT 24	Mar 26 04:18:58 PM PDT 24	5715684600 ps
T644	/workspace/coverage/default/2.chip_sw_plic_sw_irq.661105341			Mar 26 04:02:49 PM PDT 24	Mar 26 04:06:34 PM PDT 24	2759029400 ps
T336	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.307013602			Mar 26 04:00:54 PM PDT 24	Mar 26 04:05:08 PM PDT 24	2172449568 ps
T339	/workspace/coverage/default/89.chip_sw_all_escalation_resets.3273410142			Mar 26 04:12:52 PM PDT 24	Mar 26 04:24:37 PM PDT 24	4536921128 ps
T163	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2687811671			Mar 26 03:59:43 PM PDT 24	Mar 26 05:35:44 PM PDT 24	48498070848 ps
T839	/workspace/coverage/default/1.rom_e2e_static_critical.2504108464			Mar 26 03:56:09 PM PDT 24	Mar 26 04:41:30 PM PDT 24	11305591988 ps
T840	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3774621633			Mar 26 03:47:39 PM PDT 24	Mar 26 03:52:11 PM PDT 24	3257827736 ps
T214	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3710966304			Mar 26 03:48:46 PM PDT 24	Mar 26 03:56:38 PM PDT 24	4156912402 ps
T841	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.900042286			Mar 26 04:04:33 PM PDT 24	Mar 26 04:14:02 PM PDT 24	3555229332 ps
T362	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.822521154			Mar 26 04:08:45 PM PDT 24	Mar 26 04:15:12 PM PDT 24	3710277028 ps
T276	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1819113181			Mar 26 03:44:50 PM PDT 24	Mar 26 03:53:52 PM PDT 24	4764123180 ps
T213	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3096982928			Mar 26 04:04:05 PM PDT 24	Mar 26 04:13:45 PM PDT 24	4224196680 ps
T842	/workspace/coverage/default/1.chip_sw_example_manufacturer.175332915			Mar 26 03:49:50 PM PDT 24	Mar 26 03:54:36 PM PDT 24	2596898152 ps
T843	/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3061750516			Mar 26 04:09:27 PM PDT 24	Mar 26 04:40:55 PM PDT 24	9040656636 ps
T81	/workspace/coverage/default/5.chip_sw_all_escalation_resets.953594174			Mar 26 04:07:02 PM PDT 24	Mar 26 04:17:57 PM PDT 24	5251463450 ps
T251	/workspace/coverage/default/78.chip_sw_all_escalation_resets.2227226769			Mar 26 04:11:50 PM PDT 24	Mar 26 04:22:22 PM PDT 24	5513723960 ps
T260	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.778998967			Mar 26 03:58:26 PM PDT 24	Mar 26 04:00:46 PM PDT 24	3008541260 ps
T215	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2046167822			Mar 26 04:01:03 PM PDT 24	Mar 26 04:08:17 PM PDT 24	3861447730 ps
T844	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2724270054			Mar 26 04:06:32 PM PDT 24	Mar 26 04:24:34 PM PDT 24	10366236851 ps
T654	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.581947650			Mar 26 04:08:38 PM PDT 24	Mar 26 04:15:08 PM PDT 24	3988763134 ps
T415	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3441105478			Mar 26 03:52:16 PM PDT 24	Mar 26 04:13:38 PM PDT 24	5318549098 ps
T845	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2322428220			Mar 26 03:48:19 PM PDT 24	Mar 26 04:06:06 PM PDT 24	5415396209 ps
T277	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1305400496			Mar 26 03:50:21 PM PDT 24	Mar 26 04:00:21 PM PDT 24	4303197439 ps
T236	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2592650728			Mar 26 04:13:58 PM PDT 24	Mar 26 04:20:54 PM PDT 24	4036470750 ps
T261	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2048254061			Mar 26 04:10:45 PM PDT 24	Mar 26 04:42:23 PM PDT 24	9035412800 ps
T262	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3750992164			Mar 26 03:58:30 PM PDT 24	Mar 26 04:48:15 PM PDT 24	10021446496 ps
T283	/workspace/coverage/default/2.rom_keymgr_functest.1366185172			Mar 26 04:05:01 PM PDT 24	Mar 26 04:12:44 PM PDT 24	4269714950 ps
T284	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2308633385			Mar 26 04:10:01 PM PDT 24	Mar 26 04:20:01 PM PDT 24	5892358408 ps
T77	/workspace/coverage/default/1.chip_jtag_mem_access.358009747			Mar 26 03:42:29 PM PDT 24	Mar 26 04:09:04 PM PDT 24	13623705080 ps
T285	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1581992572			Mar 26 04:01:56 PM PDT 24	Mar 26 04:32:46 PM PDT 24	8441641800 ps
T286	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3065105605			Mar 26 04:07:44 PM PDT 24	Mar 26 04:39:02 PM PDT 24	12771734077 ps
T287	/workspace/coverage/default/99.chip_sw_all_escalation_resets.1515470899			Mar 26 04:13:52 PM PDT 24	Mar 26 04:21:57 PM PDT 24	5148224144 ps
T288	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2784351340			Mar 26 04:11:22 PM PDT 24	Mar 26 04:23:14 PM PDT 24	5728592344 ps
T343	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.859567565			Mar 26 03:52:08 PM PDT 24	Mar 26 03:57:44 PM PDT 24	3253524820 ps
T55	/workspace/coverage/default/1.chip_sw_alert_test.1882651099			Mar 26 03:51:28 PM PDT 24	Mar 26 03:56:31 PM PDT 24	3152520580 ps
T112	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.529555023			Mar 26 03:46:39 PM PDT 24	Mar 26 04:20:37 PM PDT 24	11161977469 ps
T846	/workspace/coverage/default/2.chip_sw_aes_enc.2081950696			Mar 26 04:00:21 PM PDT 24	Mar 26 04:04:13 PM PDT 24	2118197160 ps
T263	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1576842228			Mar 26 03:46:40 PM PDT 24	Mar 26 03:48:31 PM PDT 24	2858383854 ps
T847	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.518432949			Mar 26 03:51:57 PM PDT 24	Mar 26 04:15:16 PM PDT 24	7112290584 ps
T848	/workspace/coverage/default/1.chip_sw_plic_sw_irq.2967249230			Mar 26 03:52:56 PM PDT 24	Mar 26 03:56:58 PM PDT 24	2509556806 ps
T849	/workspace/coverage/default/0.rom_e2e_static_critical.45985761			Mar 26 03:52:40 PM PDT 24	Mar 26 04:35:08 PM PDT 24	10859538808 ps
T850	/workspace/coverage/default/1.chip_sw_example_concurrency.2951433561			Mar 26 03:48:12 PM PDT 24	Mar 26 03:53:19 PM PDT 24	2351883770 ps
T44	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.770778795			Mar 26 03:46:49 PM PDT 24	Mar 26 03:51:40 PM PDT 24	2398810104 ps
T391	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.148184100			Mar 26 04:09:45 PM PDT 24	Mar 26 04:13:53 PM PDT 24	2413847536 ps
T392	/workspace/coverage/default/1.rom_keymgr_functest.2521892143			Mar 26 03:54:15 PM PDT 24	Mar 26 04:03:32 PM PDT 24	4586821560 ps
T393	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.773167617			Mar 26 04:02:47 PM PDT 24	Mar 26 04:06:35 PM PDT 24	2811418703 ps
T394	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1183106433			Mar 26 03:48:52 PM PDT 24	Mar 26 04:00:30 PM PDT 24	8220636360 ps
T302	/workspace/coverage/default/0.chip_plic_all_irqs_20.160180256			Mar 26 03:47:26 PM PDT 24	Mar 26 03:58:41 PM PDT 24	4993288090 ps
T67	/workspace/coverage/default/2.chip_tap_straps_rma.504702636			Mar 26 04:02:30 PM PDT 24	Mar 26 04:10:35 PM PDT 24	4923795592 ps
T156	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1983217412			Mar 26 03:48:19 PM PDT 24	Mar 26 03:50:16 PM PDT 24	1683775084 ps
T395	/workspace/coverage/default/94.chip_sw_all_escalation_resets.3445321860			Mar 26 04:14:54 PM PDT 24	Mar 26 04:23:24 PM PDT 24	5272927872 ps
T278	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.365842100			Mar 26 03:49:31 PM PDT 24	Mar 26 03:58:53 PM PDT 24	4812612298 ps
T252	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3061226748			Mar 26 03:59:33 PM PDT 24	Mar 26 04:13:14 PM PDT 24	5062017880 ps
T851	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2508496037			Mar 26 04:07:29 PM PDT 24	Mar 26 04:24:09 PM PDT 24	7526496274 ps
T685	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3664096907			Mar 26 04:11:27 PM PDT 24	Mar 26 04:19:16 PM PDT 24	3385792156 ps
T852	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2848248039			Mar 26 03:50:00 PM PDT 24	Mar 26 04:00:23 PM PDT 24	4021574400 ps
T22	/workspace/coverage/default/0.chip_sw_usbdev_config_host.2759544997			Mar 26 03:47:12 PM PDT 24	Mar 26 04:19:32 PM PDT 24	8423144824 ps
T33	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1122268931			Mar 26 03:57:48 PM PDT 24	Mar 26 04:03:21 PM PDT 24	3345505068 ps
T186	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.677555711			Mar 26 03:46:03 PM PDT 24	Mar 26 03:55:29 PM PDT 24	4198660546 ps
T661	/workspace/coverage/default/68.chip_sw_all_escalation_resets.3489152483			Mar 26 04:12:20 PM PDT 24	Mar 26 04:21:43 PM PDT 24	4995628694 ps
T306	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3766175961			Mar 26 03:49:26 PM PDT 24	Mar 26 03:58:44 PM PDT 24	4123408425 ps
T82	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1785397210			Mar 26 04:01:45 PM PDT 24	Mar 26 04:23:28 PM PDT 24	10812752500 ps
T853	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.4007812333			Mar 26 04:10:36 PM PDT 24	Mar 26 04:32:11 PM PDT 24	11126347100 ps
T222	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1673656341			Mar 26 03:58:32 PM PDT 24	Mar 26 05:26:00 PM PDT 24	49416503708 ps
T854	/workspace/coverage/default/2.chip_sw_uart_smoketest.568740104			Mar 26 04:06:29 PM PDT 24	Mar 26 04:12:16 PM PDT 24	2807831696 ps
T175	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.706210416			Mar 26 03:52:31 PM PDT 24	Mar 26 04:27:27 PM PDT 24	8726139012 ps
T855	/workspace/coverage/default/2.rom_e2e_asm_init_prod.3390746322			Mar 26 04:09:08 PM PDT 24	Mar 26 04:41:41 PM PDT 24	9070512448 ps
T856	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1622644732			Mar 26 03:54:20 PM PDT 24	Mar 26 04:23:10 PM PDT 24	8531947296 ps
T857	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1229060372			Mar 26 03:49:38 PM PDT 24	Mar 26 03:56:54 PM PDT 24	7718017834 ps
T420	/workspace/coverage/default/1.chip_sw_kmac_entropy.2021110638			Mar 26 03:48:44 PM PDT 24	Mar 26 03:53:20 PM PDT 24	3138453000 ps
T858	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3357484130			Mar 26 03:56:01 PM PDT 24	Mar 26 04:17:47 PM PDT 24	7083867669 ps
T68	/workspace/coverage/default/4.chip_tap_straps_testunlock0.512595805			Mar 26 04:05:27 PM PDT 24	Mar 26 04:24:34 PM PDT 24	10100045309 ps
T164	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3935222737			Mar 26 03:49:08 PM PDT 24	Mar 26 05:34:29 PM PDT 24	48450785760 ps
T754	/workspace/coverage/default/85.chip_sw_all_escalation_resets.4031136781			Mar 26 04:16:11 PM PDT 24	Mar 26 04:27:11 PM PDT 24	4183494900 ps
T859	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.164753299			Mar 26 03:47:53 PM PDT 24	Mar 26 04:09:46 PM PDT 24	13645559604 ps
T321	/workspace/coverage/default/1.chip_sw_pattgen_ios.3118871029			Mar 26 03:48:56 PM PDT 24	Mar 26 03:53:16 PM PDT 24	3350722532 ps
T416	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1097470426			Mar 26 04:07:24 PM PDT 24	Mar 26 04:13:13 PM PDT 24	3859261640 ps
T860	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.348703806			Mar 26 03:46:02 PM PDT 24	Mar 26 04:39:13 PM PDT 24	37197305420 ps
T243	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.647390410			Mar 26 03:47:37 PM PDT 24	Mar 26 03:56:37 PM PDT 24	5783444128 ps
T861	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.711907681			Mar 26 03:52:50 PM PDT 24	Mar 26 03:59:33 PM PDT 24	4234632928 ps