Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	468	1			T421	2		T476	4		T390	3
all_values[1]	425	1			T126	1		T507	2		T421	1
all_values[2]	446	1			T476	1		T390	1		T422	4
all_values[3]	445	1			T126	1		T686	1		T476	5
all_values[4]	415	1			T421	3		T476	3		T390	1
all_values[5]	466	1			T126	1		T507	1		T421	4
all_values[6]	440	1			T126	3		T507	1		T421	2
all_values[7]	444	1			T126	1		T421	1		T422	3
all_values[8]	459	1			T686	1		T476	2		T390	3
all_values[9]	455	1			T421	3		T476	4		T389	1
all_values[10]	515	1			T421	1		T476	1		T390	1
all_values[11]	460	1			T126	2		T421	2		T476	1
all_values[12]	469	1			T126	3		T507	1		T421	3
all_values[13]	482	1			T507	1		T421	5		T476	3
all_values[14]	489	1			T421	2		T476	2		T390	1
all_values[15]	463	1			T126	1		T421	5		T476	4
all_values[16]	456	1			T126	1		T421	4		T476	3
all_values[17]	474	1			T421	5		T476	1		T390	2
all_values[18]	435	1			T507	1		T421	2		T476	1
all_values[19]	443	1			T421	1		T476	6		T390	1
all_values[20]	504	1			T126	1		T421	1		T476	5
all_values[21]	475	1			T126	1		T476	3		T422	2
all_values[22]	457	1			T421	1		T476	1		T390	1
all_values[23]	487	1			T507	2		T686	1		T421	3
all_values[24]	422	1			T126	2		T507	2		T421	1
all_values[25]	505	1			T421	1		T476	3		T422	3
all_values[26]	432	1			T507	1		T686	1		T421	5
all_values[27]	436	1			T126	2		T686	1		T421	1
all_values[28]	448	1			T126	2		T421	4		T476	4
all_values[29]	480	1			T476	2		T390	4		T422	3
all_values[30]	456	1			T126	1		T421	2		T476	2
all_values[31]	435	1			T421	3		T476	3		T422	1
all_values[32]	457	1			T421	2		T476	2		T390	1
all_values[33]	460	1			T507	1		T421	2		T476	2
all_values[34]	489	1			T507	1		T421	4		T476	4
all_values[35]	474	1			T421	1		T422	4		T389	2
all_values[36]	479	1			T507	1		T686	1		T421	1
all_values[37]	465	1			T126	1		T507	2		T421	3
all_values[38]	482	1			T421	3		T476	1		T390	1
all_values[39]	425	1			T126	1		T421	3		T422	2
all_values[40]	498	1			T421	1		T476	5		T390	2
all_values[41]	488	1			T126	2		T421	2		T476	2
all_values[42]	464	1			T507	1		T421	1		T476	2
all_values[43]	475	1			T421	1		T476	7		T422	4
all_values[44]	480	1			T126	1		T421	3		T476	3
all_values[45]	525	1			T126	2		T421	3		T476	1
all_values[46]	429	1			T421	1		T476	3		T422	2
all_values[47]	508	1			T686	1		T421	5		T476	4
all_values[48]	471	1			T421	2		T476	1		T390	4
all_values[49]	471	1			T126	1		T507	2		T421	3