Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3608	1			T126	7		T442	2		T421	14
all_values[1]	3528	1			T126	7		T442	3		T421	8
all_values[2]	3598	1			T126	12		T442	4		T421	12
all_values[3]	3580	1			T126	2		T442	1		T421	16
all_values[4]	3543	1			T126	15		T442	3		T421	16
all_values[5]	3492	1			T126	12		T442	2		T421	5
all_values[6]	3506	1			T126	10		T442	3		T421	11
all_values[7]	3579	1			T126	8		T442	2		T421	12
all_values[8]	3654	1			T126	12		T442	2		T421	14
all_values[9]	3553	1			T126	8		T442	2		T421	20
all_values[10]	3662	1			T126	10		T442	5		T421	9
all_values[11]	3560	1			T126	8		T442	1		T421	9
all_values[12]	3582	1			T126	14		T442	3		T421	16
all_values[13]	3605	1			T126	15		T442	5		T421	12
all_values[14]	3500	1			T126	11		T442	3		T421	16
all_values[15]	3674	1			T126	5		T442	4		T421	11
all_values[16]	3609	1			T126	12		T442	1		T421	9
all_values[17]	3550	1			T126	16		T442	5		T421	11
all_values[18]	3593	1			T126	11		T442	8		T421	9
all_values[19]	3591	1			T126	6		T442	2		T421	14
all_values[20]	3585	1			T126	11		T442	2		T421	11
all_values[21]	3478	1			T126	7		T442	1		T421	7
all_values[22]	3606	1			T126	13		T442	4		T421	14
all_values[23]	3548	1			T126	11		T421	11		T476	32
all_values[24]	3647	1			T126	13		T442	3		T421	16
all_values[25]	3526	1			T126	8		T442	4		T421	10
all_values[26]	3610	1			T126	13		T442	1		T421	15
all_values[27]	3682	1			T126	7		T442	6		T421	13
all_values[28]	3616	1			T126	9		T442	5		T421	11
all_values[29]	3648	1			T126	12		T442	1		T421	14
all_values[30]	3625	1			T126	11		T442	2		T421	12
all_values[31]	3689	1			T126	8		T442	3		T421	16
all_values[32]	3546	1			T126	9		T442	3		T421	16
all_values[33]	3502	1			T126	11		T442	3		T421	9
all_values[34]	3628	1			T126	9		T442	2		T421	13
all_values[35]	3621	1			T126	7		T442	4		T421	14
all_values[36]	3630	1			T126	9		T442	2		T421	14
all_values[37]	3425	1			T126	5		T442	3		T421	7
all_values[38]	3551	1			T126	10		T442	1		T421	12
all_values[39]	3590	1			T126	11		T442	6		T421	20
all_values[40]	3641	1			T126	14		T442	6		T421	23
all_values[41]	3499	1			T126	22		T442	2		T421	11
all_values[42]	3526	1			T126	6		T442	2		T421	10
all_values[43]	3570	1			T126	16		T442	2		T421	12
all_values[44]	3612	1			T126	9		T442	1		T421	12
all_values[45]	3479	1			T126	7		T442	2		T421	13
all_values[46]	3564	1			T126	13		T442	4		T421	14
all_values[47]	3579	1			T126	7		T442	1		T421	8
all_values[48]	3638	1			T126	12		T442	1		T421	11
all_values[49]	3530	1			T126	8		T442	3		T421	13
all_values[50]	3593	1			T126	7		T442	1		T421	9
all_values[51]	3595	1			T126	12		T442	6		T421	7
all_values[52]	3584	1			T126	7		T442	3		T421	8
all_values[53]	3562	1			T126	5		T442	3		T421	15
all_values[54]	3589	1			T126	11		T442	2		T421	10
all_values[55]	3551	1			T126	11		T442	3		T421	12
all_values[56]	3563	1			T126	10		T442	4		T421	9
all_values[57]	3563	1			T126	6		T442	5		T421	13
all_values[58]	3502	1			T126	14		T442	1		T421	17
all_values[59]	3506	1			T126	14		T442	5		T421	8
all_values[60]	3560	1			T126	6		T442	5		T421	13
all_values[61]	3617	1			T126	16		T442	5		T421	10
all_values[62]	3617	1			T126	9		T442	1		T421	10
all_values[63]	3698	1			T126	10		T442	2		T421	12