| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 59.38 | 67.31 | 64.84 | 36.65 | 75.78 | 85.61 | 26.10 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 50.10 | 50.10 | 52.45 | 52.45 | 55.74 | 55.74 | 23.41 | 23.41 | 70.91 | 70.91 | 85.58 | 85.58 | 12.50 | 12.50 | /workspace/coverage/default/1.chip_jtag_csr_rw.1319901816 | ||
| 56.91 | 6.81 | 66.40 | 13.95 | 63.18 | 7.44 | 31.41 | 8.00 | 74.75 | 3.84 | 85.77 | 0.18 | 19.96 | 7.46 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1537621744 | ||
| 58.15 | 1.24 | 66.53 | 0.13 | 63.47 | 0.29 | 33.15 | 1.74 | 74.75 | 0.00 | 85.77 | 0.00 | 25.22 | 5.26 | /workspace/coverage/default/0.chip_jtag_csr_rw.4002150620 | ||
| 58.91 | 0.76 | 66.99 | 0.46 | 64.73 | 1.26 | 34.10 | 0.95 | 75.77 | 1.02 | 85.77 | 0.00 | 26.10 | 0.88 | /workspace/coverage/default/2.chip_jtag_csr_rw.2672336775 | ||
| 59.28 | 0.37 | 67.01 | 0.03 | 64.76 | 0.04 | 36.28 | 2.18 | 75.78 | 0.01 | 85.77 | 0.00 | 26.10 | 0.00 | /workspace/coverage/default/1.chip_jtag_mem_access.3847245303 | ||
| 59.32 | 0.04 | 67.03 | 0.01 | 64.81 | 0.05 | 36.47 | 0.19 | 75.78 | 0.00 | 85.77 | 0.00 | 26.10 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1934454898 | ||
| 59.34 | 0.02 | 67.03 | 0.00 | 64.82 | 0.01 | 36.59 | 0.12 | 75.78 | 0.00 | 85.77 | 0.00 | 26.10 | 0.00 | /workspace/coverage/default/0.chip_jtag_mem_access.3188750592 | ||
| 59.35 | 0.01 | 67.03 | 0.00 | 64.83 | 0.02 | 36.62 | 0.03 | 75.78 | 0.00 | 85.77 | 0.00 | 26.10 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2456628550 | ||
| 59.36 | 0.01 | 67.03 | 0.00 | 64.83 | 0.00 | 36.65 | 0.03 | 75.78 | 0.00 | 85.77 | 0.00 | 26.10 | 0.00 | /workspace/coverage/default/2.chip_jtag_mem_access.713609639 | ||
| 59.36 | 0.01 | 67.03 | 0.00 | 64.84 | 0.01 | 36.65 | 0.01 | 75.78 | 0.00 | 85.77 | 0.00 | 26.10 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1342457316 | ||
| 59.36 | 0.01 | 67.03 | 0.00 | 64.84 | 0.00 | 36.65 | 0.01 | 75.78 | 0.00 | 85.77 | 0.00 | 26.10 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1420178180 | ||
| Name |
|---|
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4008450241 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2365296118 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2675241241 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1264601113 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4144645603 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.chip_jtag_csr_rw.1319901816 | Apr 02 03:44:24 PM PDT 24 | Apr 02 04:13:11 PM PDT 24 | 18674474000 ps | ||
| T2 | /workspace/coverage/default/0.chip_jtag_mem_access.3188750592 | Apr 02 03:42:08 PM PDT 24 | Apr 02 04:01:53 PM PDT 24 | 13058830540 ps | ||
| T3 | /workspace/coverage/default/2.chip_jtag_mem_access.713609639 | Apr 02 03:46:39 PM PDT 24 | Apr 02 04:03:47 PM PDT 24 | 13325590590 ps | ||
| T7 | /workspace/coverage/default/1.chip_jtag_mem_access.3847245303 | Apr 02 03:44:22 PM PDT 24 | Apr 02 04:02:10 PM PDT 24 | 13303093916 ps | ||
| T9 | /workspace/coverage/default/2.chip_jtag_csr_rw.2672336775 | Apr 02 03:46:39 PM PDT 24 | Apr 02 04:02:39 PM PDT 24 | 12383447576 ps | ||
| T8 | /workspace/coverage/default/0.chip_jtag_csr_rw.4002150620 | Apr 02 03:42:06 PM PDT 24 | Apr 02 03:53:09 PM PDT 24 | 9639032660 ps | ||
| T4 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1537621744 | Apr 02 03:41:25 PM PDT 24 | Apr 02 03:45:36 PM PDT 24 | 4195087554 ps | ||
| T5 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1342457316 | Apr 02 03:41:27 PM PDT 24 | Apr 02 03:46:58 PM PDT 24 | 5805453815 ps | ||
| T6 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2365296118 | Apr 02 03:41:31 PM PDT 24 | Apr 02 03:45:47 PM PDT 24 | 5034896118 ps | ||
| T10 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2675241241 | Apr 02 03:41:36 PM PDT 24 | Apr 02 03:45:02 PM PDT 24 | 4406559388 ps | ||
| T12 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4144645603 | Apr 02 03:41:34 PM PDT 24 | Apr 02 03:44:55 PM PDT 24 | 3565915213 ps | ||
| T13 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1934454898 | Apr 02 03:41:36 PM PDT 24 | Apr 02 03:45:06 PM PDT 24 | 4900789335 ps | ||
| T11 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4008450241 | Apr 02 03:41:25 PM PDT 24 | Apr 02 03:44:59 PM PDT 24 | 3937158864 ps | ||
| T14 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1420178180 | Apr 02 03:41:35 PM PDT 24 | Apr 02 03:45:33 PM PDT 24 | 5340340904 ps | ||
| T15 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2456628550 | Apr 02 03:41:27 PM PDT 24 | Apr 02 03:45:35 PM PDT 24 | 4602023392 ps | ||
| T16 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1264601113 | Apr 02 03:41:25 PM PDT 24 | Apr 02 03:44:57 PM PDT 24 | 4358312304 ps |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.1319901816 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 18674474000 ps |
| CPU time | 1726.33 seconds |
| Started | Apr 02 03:44:24 PM PDT 24 |
| Finished | Apr 02 04:13:11 PM PDT 24 |
| Peak memory | 594056 kb |
| Host | smart-d6caf42e-ec7a-4fa0-a4f2-6d8f112703e3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319901816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1319901816 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1537621744 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4195087554 ps |
| CPU time | 251.22 seconds |
| Started | Apr 02 03:41:25 PM PDT 24 |
| Finished | Apr 02 03:45:36 PM PDT 24 |
| Peak memory | 636656 kb |
| Host | smart-5c4e2577-13ff-4d57-b496-9655523a3264 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537621744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.1537621744 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.4002150620 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9639032660 ps |
| CPU time | 662.09 seconds |
| Started | Apr 02 03:42:06 PM PDT 24 |
| Finished | Apr 02 03:53:09 PM PDT 24 |
| Peak memory | 592180 kb |
| Host | smart-a8c8bd89-d249-4828-ac81-2531a1f54643 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002150620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.4002150620 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.2672336775 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12383447576 ps |
| CPU time | 959.9 seconds |
| Started | Apr 02 03:46:39 PM PDT 24 |
| Finished | Apr 02 04:02:39 PM PDT 24 |
| Peak memory | 592992 kb |
| Host | smart-2e8fe848-89d6-4f7c-976c-596d599c1ae8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672336775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.2672336775 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.3847245303 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13303093916 ps |
| CPU time | 1067.34 seconds |
| Started | Apr 02 03:44:22 PM PDT 24 |
| Finished | Apr 02 04:02:10 PM PDT 24 |
| Peak memory | 600416 kb |
| Host | smart-3d99aabc-c889-4697-b46a-c8e5ad99b986 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847245303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3 847245303 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1934454898 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4900789335 ps |
| CPU time | 208.85 seconds |
| Started | Apr 02 03:41:36 PM PDT 24 |
| Finished | Apr 02 03:45:06 PM PDT 24 |
| Peak memory | 637476 kb |
| Host | smart-3e0deb0c-4a3e-43dd-bdfd-bf359d363934 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934454898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.1934454898 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.3188750592 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13058830540 ps |
| CPU time | 1184.86 seconds |
| Started | Apr 02 03:42:08 PM PDT 24 |
| Finished | Apr 02 04:01:53 PM PDT 24 |
| Peak memory | 600344 kb |
| Host | smart-f7b3bef9-4a0c-4004-9900-29c03f7f33c5 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188750592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 188750592 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2456628550 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4602023392 ps |
| CPU time | 247.28 seconds |
| Started | Apr 02 03:41:27 PM PDT 24 |
| Finished | Apr 02 03:45:35 PM PDT 24 |
| Peak memory | 637472 kb |
| Host | smart-1d5b79e1-5c86-47b6-bcab-8a5c5d1971f0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456628550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.2456628550 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.713609639 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13325590590 ps |
| CPU time | 1028.21 seconds |
| Started | Apr 02 03:46:39 PM PDT 24 |
| Finished | Apr 02 04:03:47 PM PDT 24 |
| Peak memory | 600372 kb |
| Host | smart-d4d0d5e4-d95e-4e82-bacc-a2cbb19313e8 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713609639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.713609639 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1342457316 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5805453815 ps |
| CPU time | 330.66 seconds |
| Started | Apr 02 03:41:27 PM PDT 24 |
| Finished | Apr 02 03:46:58 PM PDT 24 |
| Peak memory | 637448 kb |
| Host | smart-8635b5ae-0f7a-4760-9bbd-5dd8b6f255a5 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342457316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.1342457316 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1420178180 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5340340904 ps |
| CPU time | 237.72 seconds |
| Started | Apr 02 03:41:35 PM PDT 24 |
| Finished | Apr 02 03:45:33 PM PDT 24 |
| Peak memory | 637396 kb |
| Host | smart-5dd282ca-1736-4cda-89bb-67a1825aec98 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420178180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.1420178180 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4008450241 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3937158864 ps |
| CPU time | 214.32 seconds |
| Started | Apr 02 03:41:25 PM PDT 24 |
| Finished | Apr 02 03:44:59 PM PDT 24 |
| Peak memory | 635776 kb |
| Host | smart-38a20237-7231-4b29-afd1-f87fa1d6cc71 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008450241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.4008450241 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2365296118 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5034896118 ps |
| CPU time | 255.87 seconds |
| Started | Apr 02 03:41:31 PM PDT 24 |
| Finished | Apr 02 03:45:47 PM PDT 24 |
| Peak memory | 637368 kb |
| Host | smart-44cdb2e4-310f-4ecb-906b-6470c4d3524a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365296118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.2365296118 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2675241241 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4406559388 ps |
| CPU time | 204.93 seconds |
| Started | Apr 02 03:41:36 PM PDT 24 |
| Finished | Apr 02 03:45:02 PM PDT 24 |
| Peak memory | 637344 kb |
| Host | smart-2727d009-6255-432c-8919-db4b8424463c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675241241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.2675241241 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1264601113 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4358312304 ps |
| CPU time | 212.03 seconds |
| Started | Apr 02 03:41:25 PM PDT 24 |
| Finished | Apr 02 03:44:57 PM PDT 24 |
| Peak memory | 637428 kb |
| Host | smart-ae54f0d6-b013-420f-baa2-1abb552328bb |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264601113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1264601113 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4144645603 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3565915213 ps |
| CPU time | 200.21 seconds |
| Started | Apr 02 03:41:34 PM PDT 24 |
| Finished | Apr 02 03:44:55 PM PDT 24 |
| Peak memory | 637340 kb |
| Host | smart-9088c939-4928-474a-a815-b3194415b621 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144645603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.4144645603 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
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