Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3695298	1			T5	565		T6	1552		T7	2261
values[2]	723356	1			T5	61		T6	487		T7	143
values[3]	97054	1			T5	3		T6	9		T7	4
values[4]	51058	1			T5	4		T18	261		T336	4
values[5]	34497	1			T5	1		T18	143		T336	4
values[6]	26433	1			T5	2		T18	83		T336	4
values[7]	21805	1			T5	1		T18	36		T336	4
values[8]	18540	1			T5	4		T18	15		T336	4
values[9]	16646	1			T5	2		T18	14		T336	4
values[10]	15234	1			T5	3		T18	7		T336	4
values[11]	13783	1			T5	2		T18	8		T336	4
values[12]	13133	1			T5	2		T18	7		T336	4
values[13]	12186	1			T5	1		T18	10		T336	4
values[14]	11373	1			T5	2		T18	5		T336	4
values[15]	10992	1			T5	1		T18	3		T336	4
values[16]	10645	1			T5	2		T18	2		T336	4
values[17]	10324	1			T5	2		T18	2		T336	4
values[18]	10032	1			T5	1		T18	1		T336	4
values[19]	9705	1			T5	1		T18	3		T336	4
values[20]	9444	1			T5	1		T18	7		T336	4
values[21]	9167	1			T5	1		T18	4		T336	4
values[22]	8851	1			T5	6		T18	4		T336	4
values[23]	8615	1			T5	7		T18	3		T336	4
values[24]	8377	1			T5	3		T18	1		T336	4
values[25]	7847	1			T5	1		T18	2		T336	5
values[26]	7676	1			T5	1		T18	2		T336	4
values[27]	7311	1			T5	3		T18	1		T336	4
values[28]	7049	1			T5	1		T336	4		T249	12
values[29]	6580	1			T5	2		T336	4		T249	12
values[30]	6151	1			T5	4		T336	4		T249	13
values[31]	5799	1			T5	4		T336	4		T249	13
values[32]	5421	1			T5	3		T336	4		T249	13
values[33]	4835	1			T5	1		T336	4		T249	12
values[34]	4440	1			T5	1		T336	4		T249	12
values[35]	4132	1			T5	3		T336	4		T249	12
values[36]	3928	1			T5	3		T336	4		T249	12
values[37]	3889	1			T5	3		T336	4		T249	12
values[38]	3602	1			T5	1		T336	4		T249	12
values[39]	3555	1			T5	1		T336	4		T249	13
values[40]	3311	1			T5	2		T336	4		T249	12
values[41]	3223	1			T5	2		T336	4		T249	12
values[42]	3162	1			T5	1		T336	4		T249	12
values[43]	3060	1			T336	4		T249	12		T337	5
values[44]	3100	1			T336	4		T249	12		T337	5
values[45]	3027	1			T336	4		T249	12		T337	6
values[46]	2910	1			T336	4		T249	12		T337	5
values[47]	2845	1			T336	4		T249	12		T337	5
values[48]	2857	1			T336	4		T249	12		T337	5
values[49]	2805	1			T336	4		T249	12		T337	5
values[50]	2724	1			T336	4		T249	12		T337	5
values[51]	2699	1			T336	4		T249	12		T337	5
values[52]	2560	1			T336	4		T249	12		T337	6
values[53]	2582	1			T336	4		T249	12		T337	5
values[54]	2562	1			T336	4		T249	12		T337	5
values[55]	2582	1			T336	4		T249	12		T337	5
values[56]	2449	1			T336	4		T249	13		T337	5
values[57]	2427	1			T336	4		T249	12		T337	6
values[58]	2427	1			T336	4		T249	12		T337	5
values[59]	2301	1			T336	4		T249	12		T337	5
values[60]	2394	1			T336	4		T249	12		T337	5
values[61]	2668	1			T336	4		T249	12		T337	5
values[62]	4124	1			T336	4		T249	12		T337	5
values[63]	15694	1			T336	4		T249	172		T337	75
values[64]	226291	1			T336	726		T249	1953		T337	900

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4698578	1			T5	1377		T6	1579		T7	2452
values[2]	774049	1			T5	173		T6	362		T7	133
values[3]	75268	1			T5	6		T6	26		T7	3
values[4]	13789	1			T18	18		T125	2		T40	8
values[5]	5151	1			T336	4		T156	4		T249	18
values[6]	3169	1			T336	1		T156	4		T249	7
values[7]	2543	1			T336	1		T156	2		T249	3
values[8]	2124	1			T336	1		T249	2		T337	1
values[9]	1680	1			T336	1		T249	1		T337	1
values[10]	1501	1			T336	1		T249	1		T337	1
values[11]	1330	1			T336	1		T249	1		T337	1
values[12]	1388	1			T336	1		T249	1		T337	1
values[13]	1330	1			T336	1		T249	1		T337	1
values[14]	1295	1			T336	1		T249	1		T337	1
values[15]	1218	1			T336	1		T249	1		T337	1
values[16]	1086	1			T336	1		T249	1		T337	1
values[17]	1007	1			T336	1		T249	1		T337	1
values[18]	928	1			T336	1		T249	1		T337	1
values[19]	956	1			T336	1		T249	1		T337	1
values[20]	973	1			T336	1		T249	1		T337	1
values[21]	943	1			T336	1		T249	1		T337	1
values[22]	858	1			T336	1		T249	1		T337	1
values[23]	748	1			T336	1		T249	1		T337	1
values[24]	698	1			T336	1		T249	1		T337	1
values[25]	746	1			T336	1		T249	1		T337	1
values[26]	718	1			T336	1		T249	1		T337	1
values[27]	656	1			T336	1		T249	1		T337	1
values[28]	625	1			T336	1		T249	1		T337	1
values[29]	628	1			T336	1		T249	1		T337	1
values[30]	590	1			T336	1		T249	1		T337	1
values[31]	556	1			T336	1		T249	1		T337	1
values[32]	584	1			T336	1		T249	1		T337	1
values[33]	514	1			T336	1		T249	1		T337	1
values[34]	508	1			T336	1		T249	1		T337	1
values[35]	571	1			T336	1		T249	1		T337	1
values[36]	529	1			T336	1		T249	1		T337	1
values[37]	504	1			T336	1		T249	1		T337	1
values[38]	499	1			T336	1		T249	1		T337	1
values[39]	443	1			T336	1		T249	1		T337	1
values[40]	432	1			T336	1		T249	1		T337	1
values[41]	450	1			T336	1		T249	1		T337	1
values[42]	442	1			T336	1		T249	1		T337	1
values[43]	409	1			T336	1		T249	1		T337	1
values[44]	392	1			T336	1		T249	1		T337	1
values[45]	396	1			T336	1		T249	1		T337	1
values[46]	379	1			T336	1		T249	2		T337	1
values[47]	370	1			T336	1		T249	1		T337	1
values[48]	375	1			T336	1		T249	1		T337	1
values[49]	365	1			T336	1		T249	1		T337	1
values[50]	339	1			T336	1		T249	1		T337	1
values[51]	336	1			T336	1		T249	1		T337	1
values[52]	343	1			T336	1		T249	1		T337	1
values[53]	335	1			T336	1		T249	1		T337	1
values[54]	334	1			T336	1		T249	1		T337	1
values[55]	332	1			T336	1		T249	1		T337	1
values[56]	351	1			T336	1		T249	1		T337	1
values[57]	345	1			T336	1		T249	1		T337	1
values[58]	375	1			T336	1		T249	1		T337	1
values[59]	361	1			T336	1		T249	1		T337	1
values[60]	317	1			T336	1		T249	1		T337	1
values[61]	391	1			T336	1		T249	1		T337	1
values[62]	667	1			T336	1		T249	1		T337	1
values[63]	3097	1			T336	1		T249	14		T337	19
values[64]	25370	1			T336	198		T249	177		T337	182

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	608541	1			T5	180		T6	37		T7	694
values[2]	2586565	1			T5	414		T6	1409		T7	1649
values[3]	1139933	1			T5	50		T6	613		T7	219
values[4]	146693	1			T5	13		T6	15		T7	4
values[5]	75320	1			T5	3		T18	216		T336	4
values[6]	48427	1			T5	2		T18	145		T336	4
values[7]	34747	1			T5	1		T18	64		T336	4
values[8]	27180	1			T5	1		T18	37		T336	4
values[9]	22458	1			T5	2		T18	21		T336	4
values[10]	19893	1			T5	2		T18	16		T336	4
values[11]	17885	1			T5	2		T18	13		T336	4
values[12]	16536	1			T5	1		T18	16		T336	4
values[13]	15402	1			T5	2		T18	12		T336	4
values[14]	14246	1			T5	3		T18	7		T336	4
values[15]	13753	1			T5	1		T18	9		T336	4
values[16]	12977	1			T5	1		T18	15		T336	4
values[17]	12514	1			T5	3		T18	14		T336	4
values[18]	12106	1			T5	1		T18	8		T336	4
values[19]	11870	1			T5	1		T18	3		T336	4
values[20]	11149	1			T5	4		T18	5		T336	4
values[21]	10856	1			T5	5		T18	9		T336	4
values[22]	10670	1			T5	1		T18	6		T336	4
values[23]	10365	1			T5	4		T18	6		T336	4
values[24]	9737	1			T5	4		T18	3		T336	4
values[25]	9082	1			T5	4		T18	8		T336	4
values[26]	8511	1			T5	6		T18	9		T336	4
values[27]	8117	1			T5	6		T18	8		T336	4
values[28]	7780	1			T5	3		T18	10		T336	4
values[29]	7334	1			T5	6		T18	7		T336	4
values[30]	6928	1			T5	5		T18	2		T336	4
values[31]	6498	1			T5	2		T336	4		T156	4
values[32]	6134	1			T5	3		T336	4		T156	1
values[33]	5440	1			T5	1		T336	4		T156	3
values[34]	5006	1			T5	1		T336	4		T156	2
values[35]	4771	1			T5	1		T336	4		T156	4
values[36]	4726	1			T5	2		T336	4		T156	4
values[37]	4350	1			T5	4		T336	4		T156	4
values[38]	4200	1			T5	1		T336	4		T156	4
values[39]	3947	1			T5	3		T336	4		T156	3
values[40]	3822	1			T336	4		T156	2		T249	12
values[41]	3651	1			T336	4		T156	6		T249	12
values[42]	3455	1			T336	4		T156	1		T249	12
values[43]	3442	1			T336	4		T156	3		T249	12
values[44]	3438	1			T336	4		T156	4		T249	12
values[45]	3474	1			T336	4		T156	3		T249	12
values[46]	3360	1			T336	4		T156	4		T249	12
values[47]	3153	1			T336	5		T156	1		T249	13
values[48]	3131	1			T336	4		T249	12		T337	5
values[49]	3141	1			T336	5		T249	12		T337	5
values[50]	3010	1			T336	4		T249	12		T337	5
values[51]	2936	1			T336	4		T249	12		T337	5
values[52]	2982	1			T336	5		T249	14		T337	5
values[53]	2938	1			T336	5		T249	12		T337	5
values[54]	2955	1			T336	4		T249	12		T337	6
values[55]	2682	1			T336	4		T249	12		T337	5
values[56]	2703	1			T336	4		T249	12		T337	5
values[57]	2691	1			T336	4		T249	12		T337	5
values[58]	2653	1			T336	4		T249	12		T337	5
values[59]	2694	1			T336	4		T249	12		T337	5
values[60]	2621	1			T336	4		T249	13		T337	5
values[61]	2860	1			T336	4		T249	12		T337	5
values[62]	3996	1			T336	4		T249	12		T337	5
values[63]	18973	1			T336	108		T249	14		T337	9
values[64]	214389	1			T336	708		T249	2332		T337	929