Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1010522	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1712903

1

T1

39

T2

39

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2107895	1			T16	6378		T37	98		T8	4792
values[0x0]	292421	1			T1	22		T2	25		T3	13
values[0x1]	323109	1			T1	17		T2	14		T3	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	750675	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1972750

1

T1

39

T2

39

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	42436	1			T1	1		T2	1		T14	1
valid_sources[0x01]	41851	1			T3	2		T22	2		T16	170
valid_sources[0x02]	42371	1			T14	4		T16	185		T37	26
valid_sources[0x03]	42781	1			T1	1		T16	182		T37	34
valid_sources[0x04]	42574	1			T2	1		T16	189		T37	35
valid_sources[0x05]	43021	1			T1	1		T2	1		T14	1
valid_sources[0x06]	41688	1			T2	2		T16	167		T37	32
valid_sources[0x07]	42969	1			T16	172		T37	32		T8	212
valid_sources[0x08]	42138	1			T1	1		T14	1		T16	175
valid_sources[0x09]	43205	1			T2	1		T14	1		T22	4
valid_sources[0x0a]	42841	1			T1	5		T3	2		T14	3
valid_sources[0x0b]	42961	1			T2	1		T16	177		T37	32
valid_sources[0x0c]	43216	1			T1	1		T2	3		T16	175
valid_sources[0x0d]	42222	1			T1	2		T14	1		T16	158
valid_sources[0x0e]	42183	1			T2	1		T22	3		T16	168
valid_sources[0x0f]	43111	1			T3	4		T4	31		T16	165
valid_sources[0x10]	42576	1			T14	2		T22	3		T16	177
valid_sources[0x11]	42599	1			T1	1		T3	1		T14	1
valid_sources[0x12]	41670	1			T2	1		T3	3		T16	174
valid_sources[0x13]	41919	1			T1	1		T16	166		T37	28
valid_sources[0x14]	42381	1			T2	1		T14	2		T22	1
valid_sources[0x15]	41608	1			T16	147		T37	38		T8	146
valid_sources[0x16]	42201	1			T14	1		T22	2		T16	162
valid_sources[0x17]	41690	1			T14	1		T22	4		T16	185
valid_sources[0x18]	42097	1			T2	3		T3	1		T16	161
valid_sources[0x19]	42136	1			T1	4		T2	1		T16	171
valid_sources[0x1a]	42781	1			T2	1		T3	1		T16	159
valid_sources[0x1b]	42463	1			T3	1		T16	164		T37	16
valid_sources[0x1c]	42792	1			T2	2		T3	2		T16	176
valid_sources[0x1d]	44657	1			T1	1		T16	160		T37	38
valid_sources[0x1e]	41645	1			T1	2		T3	2		T16	184
valid_sources[0x1f]	43204	1			T1	3		T2	1		T3	1
valid_sources[0x20]	42767	1			T14	1		T16	177		T37	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1216368

1

T16

1523

T37

90

T8

2405

values[0x0]

all_enables

biggest_size

255358

1

T1

22

T2

25

T3

13

values[0x1]

all_enables

biggest_size

241177

1

T1

17

T2

14

T3

26

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2827199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

445971

1

T5

83

T6

286

T7

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1109537	1			T5	244		T6	742		T7	48
values[0x0]	1055912	1			T5	209		T6	643		T7	8
values[0x1]	1107721	1			T5	214		T6	663		T7	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2188653	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1084517

1

T5

203

T6

712

T7

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49392	1			T5	10		T6	18		T7	3
valid_sources[0x01]	51518	1			T5	5		T6	46		T7	2
valid_sources[0x02]	50716	1			T5	1		T6	34		T7	1
valid_sources[0x03]	50805	1			T5	27		T6	26		T7	1
valid_sources[0x04]	50654	1			T5	3		T6	42		T7	1
valid_sources[0x05]	50393	1			T5	29		T6	32		T7	2
valid_sources[0x06]	50988	1			T6	69		T7	2		T18	16
valid_sources[0x07]	51710	1			T5	1		T6	16		T7	3
valid_sources[0x08]	50827	1			T6	17		T7	2		T18	7
valid_sources[0x09]	50754	1			T5	4		T6	61		T7	1
valid_sources[0x0a]	51008	1			T6	38		T18	15		T52	6
valid_sources[0x0b]	51606	1			T5	51		T6	15		T18	11
valid_sources[0x0c]	50141	1			T5	1		T6	44		T7	1
valid_sources[0x0d]	51536	1			T5	5		T6	18		T7	2
valid_sources[0x0e]	50946	1			T5	7		T6	56		T7	4
valid_sources[0x0f]	51566	1			T5	4		T6	30		T7	1
valid_sources[0x10]	51984	1			T6	23		T7	2		T18	21
valid_sources[0x11]	50651	1			T5	13		T6	31		T7	2
valid_sources[0x12]	51067	1			T5	1		T6	15		T7	2
valid_sources[0x13]	51934	1			T5	3		T6	27		T7	2
valid_sources[0x14]	52199	1			T5	18		T6	22		T18	10
valid_sources[0x15]	50081	1			T5	6		T6	16		T7	1
valid_sources[0x16]	52141	1			T5	7		T6	34		T7	4
valid_sources[0x17]	51054	1			T5	2		T6	31		T7	2
valid_sources[0x18]	52088	1			T5	26		T6	31		T18	14
valid_sources[0x19]	51695	1			T5	4		T6	49		T7	1
valid_sources[0x1a]	50691	1			T5	5		T6	24		T7	1
valid_sources[0x1b]	51580	1			T5	30		T6	24		T7	4
valid_sources[0x1c]	51221	1			T5	17		T6	50		T18	10
valid_sources[0x1d]	51955	1			T5	49		T6	15		T7	1
valid_sources[0x1e]	49815	1			T5	3		T6	43		T7	1
valid_sources[0x1f]	50831	1			T5	11		T6	61		T7	3
valid_sources[0x20]	51466	1			T6	32		T18	20		T52	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46742

1

T5

9

T6

23

T7

5

values[0x0]

all_enables

biggest_size

352478

1

T5

67

T6

231

T7

4

values[0x1]

all_enables

biggest_size

46751

1

T5

7

T6

32

T7

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3001063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

488675

1

T5

212

T6

282

T7

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1195549	1			T5	500		T6	683		T7	68
values[0x0]	1099515	1			T5	477		T6	619		T7	5
values[0x1]	1194674	1			T5	572		T6	665		T7	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2302483	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1187255

1

T5

506

T6

656

T7

44

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53880	1			T5	8		T6	26		T7	1
valid_sources[0x01]	54712	1			T5	25		T6	20		T7	1
valid_sources[0x02]	55304	1			T5	33		T6	35		T7	1
valid_sources[0x03]	54123	1			T5	44		T6	34		T7	2
valid_sources[0x04]	55956	1			T5	31		T6	36		T7	3
valid_sources[0x05]	53937	1			T5	12		T6	34		T7	4
valid_sources[0x06]	54326	1			T5	18		T6	25		T7	2
valid_sources[0x07]	55645	1			T5	24		T6	39		T7	1
valid_sources[0x08]	54184	1			T5	20		T6	21		T7	3
valid_sources[0x09]	54308	1			T5	32		T6	26		T18	6
valid_sources[0x0a]	53895	1			T5	33		T6	29		T7	2
valid_sources[0x0b]	54367	1			T5	31		T6	45		T7	1
valid_sources[0x0c]	53857	1			T5	18		T6	32		T18	11
valid_sources[0x0d]	54383	1			T5	26		T6	29		T7	6
valid_sources[0x0e]	55358	1			T5	9		T6	32		T7	2
valid_sources[0x0f]	54597	1			T5	22		T6	32		T7	2
valid_sources[0x10]	53860	1			T5	10		T6	22		T7	1
valid_sources[0x11]	54663	1			T5	12		T6	37		T7	2
valid_sources[0x12]	54531	1			T5	31		T6	28		T7	2
valid_sources[0x13]	54427	1			T5	29		T6	28		T18	15
valid_sources[0x14]	54274	1			T5	50		T6	28		T7	3
valid_sources[0x15]	54919	1			T5	22		T6	31		T7	1
valid_sources[0x16]	54541	1			T5	13		T6	28		T7	1
valid_sources[0x17]	54511	1			T5	11		T6	30		T7	1
valid_sources[0x18]	54311	1			T5	27		T6	24		T7	1
valid_sources[0x19]	55218	1			T5	19		T6	38		T7	1
valid_sources[0x1a]	54682	1			T5	7		T6	31		T7	2
valid_sources[0x1b]	54040	1			T5	2		T6	35		T7	3
valid_sources[0x1c]	53778	1			T5	22		T6	31		T7	2
valid_sources[0x1d]	54747	1			T5	6		T6	39		T18	16
valid_sources[0x1e]	55686	1			T5	30		T6	20		T7	3
valid_sources[0x1f]	55646	1			T5	16		T6	22		T7	3
valid_sources[0x20]	54489	1			T5	18		T6	35		T18	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51422

1

T5

28

T6

27

T7

2

values[0x0]

all_enables

biggest_size

385961

1

T5

163

T6

224

T7

3

values[0x1]

all_enables

biggest_size

51292

1

T5

21

T6

31

T7

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2851293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

450375

1

T5

99

T6

306

T7

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1119052	1			T5	229		T6	703		T7	50
values[0x0]	1065087	1			T5	220		T6	639		T7	12
values[0x1]	1117529	1			T5	250		T6	732		T7	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2207934	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1093734

1

T5

235

T6

718

T7

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51590	1			T5	15		T6	38		T7	2
valid_sources[0x01]	51249	1			T5	9		T6	30		T7	2
valid_sources[0x02]	51965	1			T5	16		T6	35		T7	1
valid_sources[0x03]	51800	1			T5	19		T6	26		T7	4
valid_sources[0x04]	51375	1			T5	14		T6	39		T7	4
valid_sources[0x05]	52115	1			T5	11		T6	36		T7	2
valid_sources[0x06]	51170	1			T5	8		T6	30		T18	22
valid_sources[0x07]	51962	1			T5	3		T6	21		T7	1
valid_sources[0x08]	51577	1			T5	12		T6	34		T7	4
valid_sources[0x09]	51569	1			T5	9		T6	40		T7	1
valid_sources[0x0a]	51109	1			T5	10		T6	24		T7	2
valid_sources[0x0b]	51267	1			T5	6		T6	30		T7	1
valid_sources[0x0c]	50421	1			T5	21		T6	45		T7	1
valid_sources[0x0d]	51065	1			T5	8		T6	42		T7	1
valid_sources[0x0e]	50909	1			T5	18		T6	33		T7	1
valid_sources[0x0f]	52076	1			T5	11		T6	22		T7	1
valid_sources[0x10]	51644	1			T5	6		T6	40		T7	4
valid_sources[0x11]	51559	1			T5	4		T6	35		T7	2
valid_sources[0x12]	51344	1			T5	6		T6	42		T7	1
valid_sources[0x13]	52028	1			T5	8		T6	33		T7	2
valid_sources[0x14]	51902	1			T5	26		T6	28		T7	2
valid_sources[0x15]	52392	1			T5	10		T6	42		T7	3
valid_sources[0x16]	50826	1			T5	5		T6	37		T7	3
valid_sources[0x17]	52424	1			T5	12		T6	41		T7	2
valid_sources[0x18]	51931	1			T5	22		T6	26		T7	2
valid_sources[0x19]	51551	1			T5	1		T6	38		T7	1
valid_sources[0x1a]	51450	1			T5	5		T6	40		T7	2
valid_sources[0x1b]	51576	1			T5	10		T6	38		T7	3
valid_sources[0x1c]	51451	1			T5	23		T6	28		T7	1
valid_sources[0x1d]	52075	1			T5	8		T6	27		T7	1
valid_sources[0x1e]	51652	1			T5	18		T6	24		T18	14
valid_sources[0x1f]	52574	1			T5	6		T6	41		T18	14
valid_sources[0x20]	51176	1			T5	12		T6	26		T18	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47687

1

T5

9

T6

25

T7

3

values[0x0]

all_enables

biggest_size

355631

1

T5

78

T6

241

T7

5

values[0x1]

all_enables

biggest_size

47057

1

T5

12

T6

40

T7

2