Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
47.62			47.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_kmac	48.11			48.11

---

Module Instance : tb.dut.top_earlgrey.u_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
48.11			48.11

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
48.11			48.11

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	76	46	60.53
Total Bits	6506	3098	47.62
Total Bits 0->1	3253	1549	47.62
Total Bits 1->0	3253	1549	47.62

Ports	76	46	60.53
Port Bits	6506	3098	47.62
Port Bits 0->1	3253	1549	47.62
Port Bits 1->0	3253	1549	47.62

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[11:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[19:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T3,*T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_o.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T3,*T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T9,T10,T36	Yes	T9,T10,T36	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T9,T10,T36	Yes	T9,T10,T36	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
keymgr_key_i.valid	No	No		No		INPUT
app_i[0].last	No	No		No		INPUT
app_i[0].strb[7:0]	No	No		No		INPUT
app_i[0].data[63:0]	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
app_i[0].valid	No	No		No		INPUT
app_i[1].last	No	No		No		INPUT
app_i[1].strb[7:0]	No	No		No		INPUT
app_i[1].data[63:0]	No	No		No		INPUT
app_i[1].valid	No	No		No		INPUT
app_i[2].last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
app_i[2].strb[7:0]	No	No		No		INPUT
app_i[2].data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
app_i[2].data[63:39]	No	No		No		INPUT
app_i[2].valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
app_o[0].error	No	No		No		OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	No	No		No		OUTPUT
app_o[0].done	No	No		No		OUTPUT
app_o[0].ready	No	No		No		OUTPUT
app_o[1].error	No	No		No		OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	No	No		No		OUTPUT
app_o[1].done	No	No		No		OUTPUT
app_o[1].ready	No	No		No		OUTPUT
app_o[2].error	No	No		No		OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T14,T4,T37	Yes	T14,T4,T37	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
app_o[2].done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
app_o[2].ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
intr_kmac_done_o	Yes	Yes	T8,T10	Yes	T8,T10	OUTPUT
intr_fifo_empty_o	Yes	Yes	T10	Yes	T10	OUTPUT
intr_kmac_err_o	Yes	Yes	T13,T12	Yes	T13,T12	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_kmac

	Total	Covered	Percent
Totals	75	47	62.67
Total Bits	6440	3098	48.11
Total Bits 0->1	3220	1549	48.11
Total Bits 1->0	3220	1549	48.11

Ports	75	47	62.67
Port Bits	6440	3098	48.11
Port Bits 0->1	3220	1549	48.11
Port Bits 1->0	3220	1549	48.11

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[11:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[19:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T3,*T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_o.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T3,*T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T9,T10,T36	Yes	T9,T10,T36	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T9,T10,T36	Yes	T9,T10,T36	OUTPUT
keymgr_key_i.key[1:0][255:0]	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
keymgr_key_i.valid	No	No		No		INPUT
app_i[0].last	No	No		No		INPUT
app_i[0].strb[7:0]	No	No		No		INPUT
app_i[0].data[63:0]	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
app_i[0].valid	No	No		No		INPUT
app_i[1].last	No	No		No		INPUT
app_i[1].strb[7:0]	No	No		No		INPUT
app_i[1].data[63:0]	No	No		No		INPUT
app_i[1].valid	No	No		No		INPUT
app_i[2].last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
app_i[2].strb[7:0]	Excluded	Excluded		Excluded		INPUT	[UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
app_i[2].data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
app_i[2].data[63:39]	Excluded	Excluded		Excluded		INPUT	[UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
app_i[2].valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
app_o[0].error	No	No		No		OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	No	No		No		OUTPUT
app_o[0].done	No	No		No		OUTPUT
app_o[0].ready	No	No		No		OUTPUT
app_o[1].error	No	No		No		OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	No	No		No		OUTPUT
app_o[1].done	No	No		No		OUTPUT
app_o[1].ready	No	No		No		OUTPUT
app_o[2].error	No	No		No		OUTPUT
app_o[2].digest_share1[383:0]	Yes	Yes	T14,T4,T37	Yes	T14,T4,T37	OUTPUT
app_o[2].digest_share0[383:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
app_o[2].done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
app_o[2].ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
intr_kmac_done_o	Yes	Yes	T8,T10	Yes	T8,T10	OUTPUT
intr_fifo_empty_o	Yes	Yes	T10	Yes	T10	OUTPUT
intr_kmac_err_o	Yes	Yes	T13,T12	Yes	T13,T12	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range