Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.10 93.10

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_i2c0 92.44 92.44
tb.dut.top_earlgrey.u_i2c1 92.49 92.49
tb.dut.top_earlgrey.u_i2c2 93.06 93.06



Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.44 92.44


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.44 92.44


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.22 70.61 85.06 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.49 92.49


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.49 92.49


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.22 70.61 85.06 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.06 93.06


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.06 93.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.22 70.61 85.06 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 52 46 88.46
Total Bits 348 324 93.10
Total Bits 0->1 174 162 93.10
Total Bits 1->0 174 162 93.10

Ports 52 46 88.46
Port Bits 348 324 93.10
Port Bits 0->1 174 162 93.10
Port Bits 1->0 174 162 93.10

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T3,T4,T22 Yes T3,T4,T22 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_source[5:0] Yes Yes *T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T4,T16,T8 Yes T4,T16,T8 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
cio_scl_i Yes Yes T28,T41,T47 Yes T28,T41,T47 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
cio_sda_i Yes Yes T16,T9,T28 Yes T16,T9,T28 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
intr_fmt_threshold_o Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
intr_rx_threshold_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_acq_threshold_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_rx_overflow_o Yes Yes T8,T13,T17 Yes T8,T13,T17 OUTPUT
intr_nak_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_scl_interference_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_sda_interference_o Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
intr_stretch_timeout_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_sda_unstable_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_cmd_complete_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_tx_stretch_o Yes Yes T8,T13,T17 Yes T8,T13,T17 OUTPUT
intr_tx_threshold_o Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
intr_acq_full_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_unexp_stop_o Yes Yes T8,T10,T17 Yes T8,T10,T17 OUTPUT
intr_host_timeout_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0
TotalCoveredPercent
Totals 52 45 86.54
Total Bits 344 318 92.44
Total Bits 0->1 172 159 92.44
Total Bits 1->0 172 159 92.44

Ports 52 45 86.54
Port Bits 344 318 92.44
Port Bits 0->1 172 159 92.44
Port Bits 1->0 172 159 92.44

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_source[5:0] Yes Yes *T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T4,T16,T9 Yes T4,T16,T9 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T4,T16,T9 Yes T4,T16,T9 OUTPUT
cio_scl_i Yes Yes T28,T47,T23 Yes T28,T47,T23 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T4,T8,T11 Yes T4,T8,T11 OUTPUT
cio_sda_i Yes Yes T16,T28,T31 Yes T16,T28,T31 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T4,T16,T9 Yes T4,T16,T9 OUTPUT
intr_fmt_threshold_o Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT
intr_rx_threshold_o Yes Yes T13 Yes T13 OUTPUT
intr_acq_threshold_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_rx_overflow_o Yes Yes T12 Yes T12 OUTPUT
intr_nak_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_scl_interference_o Yes Yes T13,T12 Yes T13,T12 OUTPUT
intr_sda_interference_o Yes Yes T4,T9,T10 Yes T4,T9,T10 OUTPUT
intr_stretch_timeout_o Yes Yes T8,T10 Yes T8,T10 OUTPUT
intr_sda_unstable_o Yes Yes T8 Yes T8 OUTPUT
intr_cmd_complete_o No No No OUTPUT
intr_tx_stretch_o Yes Yes T8,T17 Yes T8,T17 OUTPUT
intr_tx_threshold_o Yes Yes T16,T9,T11 Yes T16,T9,T11 OUTPUT
intr_acq_full_o Yes Yes T8,T12 Yes T8,T12 OUTPUT
intr_unexp_stop_o Yes Yes T8,T17 Yes T8,T17 OUTPUT
intr_host_timeout_o Yes Yes T10,T13 Yes T10,T13 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1
TotalCoveredPercent
Totals 52 45 86.54
Total Bits 346 320 92.49
Total Bits 0->1 173 160 92.49
Total Bits 1->0 173 160 92.49

Ports 52 45 86.54
Port Bits 346 320 92.49
Port Bits 0->1 173 160 92.49
Port Bits 1->0 173 160 92.49

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T3,*T4,*T22 Yes T3,T4,T22 INPUT
tl_i.a_address[18:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_source[5:0] Yes Yes *T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T4,T16,T8 Yes T4,T16,T8 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
cio_scl_i Yes Yes T28,T41,T30 Yes T28,T41,T30 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT
cio_sda_i Yes Yes T28,T23,T24 Yes T28,T23,T24 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T16,T9,T20 Yes T16,T9,T20 OUTPUT
intr_fmt_threshold_o Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
intr_rx_threshold_o Yes Yes T8,T12 Yes T8,T12 OUTPUT
intr_acq_threshold_o Yes Yes T12 Yes T12 OUTPUT
intr_rx_overflow_o Yes Yes T8,T13,T12 Yes T8,T13,T12 OUTPUT
intr_nak_o Yes Yes T10 Yes T10 OUTPUT
intr_scl_interference_o Yes Yes T10,T12 Yes T10,T12 OUTPUT
intr_sda_interference_o Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT
intr_stretch_timeout_o Yes Yes T10,T13 Yes T10,T13 OUTPUT
intr_sda_unstable_o Yes Yes T8,T10,T17 Yes T8,T10,T17 OUTPUT
intr_cmd_complete_o Yes Yes T10,T17,T12 Yes T10,T17,T12 OUTPUT
intr_tx_stretch_o No No No OUTPUT
intr_tx_threshold_o Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
intr_acq_full_o Yes Yes T8,T13,T12 Yes T8,T13,T12 OUTPUT
intr_unexp_stop_o Yes Yes T8,T10,T17 Yes T8,T10,T17 OUTPUT
intr_host_timeout_o Yes Yes T8,T10 Yes T8,T10 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2
TotalCoveredPercent
Totals 52 46 88.46
Total Bits 346 322 93.06
Total Bits 0->1 173 161 93.06
Total Bits 1->0 173 161 93.06

Ports 52 46 88.46
Port Bits 346 322 93.06
Port Bits 0->1 173 161 93.06
Port Bits 1->0 173 161 93.06

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T6,T7 Yes T4,T6,T7 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T3,*T4,*T22 Yes T3,T4,T22 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T6,T7 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T6,T7 OUTPUT
tl_o.d_sink Yes Yes T6,T7,T18 Yes T5,T6,T7 OUTPUT
tl_o.d_source[5:0] Yes Yes *T4,*T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T6,T7 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T4,T16,T8 Yes T4,T16,T8 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
cio_scl_i Yes Yes T28,T23,T24 Yes T28,T23,T24 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T16,T8,T10 Yes T16,T8,T10 OUTPUT
cio_sda_i Yes Yes T9,T28,T54 Yes T9,T28,T54 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T4,T8,T9 Yes T4,T8,T9 OUTPUT
intr_fmt_threshold_o Yes Yes T4,T16,T8 Yes T4,T16,T8 OUTPUT
intr_rx_threshold_o Yes Yes T8,T10,T12 Yes T8,T10,T12 OUTPUT
intr_acq_threshold_o Yes Yes T8 Yes T8 OUTPUT
intr_rx_overflow_o Yes Yes T17 Yes T17 OUTPUT
intr_nak_o Yes Yes T8,T17 Yes T8,T17 OUTPUT
intr_scl_interference_o Yes Yes T8,T13 Yes T8,T13 OUTPUT
intr_sda_interference_o Yes Yes T8,T10,T11 Yes T8,T10,T11 OUTPUT
intr_stretch_timeout_o Yes Yes T8 Yes T8 OUTPUT
intr_sda_unstable_o Yes Yes T8,T13,T46 Yes T8,T13,T46 OUTPUT
intr_cmd_complete_o Yes Yes T8,T10,T13 Yes T8,T10,T13 OUTPUT
intr_tx_stretch_o Yes Yes T13,T17 Yes T13,T17 OUTPUT
intr_tx_threshold_o Yes Yes T4,T16,T9 Yes T4,T16,T9 OUTPUT
intr_acq_full_o Yes Yes T8,T10 Yes T8,T10 OUTPUT
intr_unexp_stop_o Yes Yes T10,T12 Yes T10,T12 OUTPUT
intr_host_timeout_o Yes Yes T8,T10 Yes T8,T10 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%