Module Definition
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Module : rv_plic
SCORELINECONDTOGGLEFSMBRANCHASSERT
36.00 2.84 0.00 97.18 0.00 80.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic 36.00 2.84 0.00 97.18 0.00 80.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
36.00 2.84 0.00 97.18 0.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.56 73.95 76.25 95.08 81.82 85.71


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.22 70.61 85.06 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 33.33 33.33
gen_target[0].u_target 41.15 0.40 39.02 58.52 66.67
u_gateway 75.00 100.00 25.00 100.00
u_prim_flop_2sync 100.00 100.00 100.00
u_reg 96.00 94.00 99.88 90.13 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_plic
Line No.TotalCoveredPercent
TOTAL563162.84
CONT_ASSIGN74100.00
ALWAYS77400.00
ALWAYS83400.00
CONT_ASSIGN99100.00
CONT_ASSIGN100100.00
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CONT_ASSIGN102100.00
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CONT_ASSIGN120100.00
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CONT_ASSIGN122100.00
CONT_ASSIGN123100.00
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CONT_ASSIGN130100.00
CONT_ASSIGN131100.00
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CONT_ASSIGN133100.00
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CONT_ASSIGN140100.00
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CONT_ASSIGN184100.00
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CONT_ASSIGN220100.00
CONT_ASSIGN221100.00
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CONT_ASSIGN223100.00
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CONT_ASSIGN230100.00
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CONT_ASSIGN240100.00
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CONT_ASSIGN243100.00
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CONT_ASSIGN292100.00
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CONT_ASSIGN298100.00
CONT_ASSIGN299100.00
CONT_ASSIGN300100.00
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
74 0 1
77 0 1
78 0 1
79 0 2
==> MISSING_ELSE
83 0 1
84 0 1
85 0 2
==> MISSING_ELSE
99 0 1
100 0 1
101 0 1
102 0 1
103 0 1
104 0 1
105 0 1
106 0 1
107 0 1
108 0 1
109 0 1
110 0 1
111 0 1
112 0 1
113 0 1
114 0 1
115 0 1
116 0 1
117 0 1
118 0 1
119 0 1
120 0 1
121 0 1
122 0 1
123 0 1
124 0 1
125 0 1
126 0 1
127 0 1
128 0 1
129 0 1
130 0 1
131 0 1
132 0 1
133 0 1
134 0 1
135 0 1
136 0 1
137 0 1
138 0 1
139 0 1
140 0 1
141 0 1
142 0 1
143 0 1
144 0 1
145 0 1
146 0 1
147 0 1
148 0 1
149 0 1
150 0 1
151 0 1
152 0 1
153 0 1
154 0 1
155 0 1
156 0 1
157 0 1
158 0 1
159 0 1
160 0 1
161 0 1
162 0 1
163 0 1
164 0 1
165 0 1
166 0 1
167 0 1
168 0 1
169 0 1
170 0 1
171 0 1
172 0 1
173 0 1
174 0 1
175 0 1
176 0 1
177 0 1
178 0 1
179 0 1
180 0 1
181 0 1
182 0 1
183 0 1
184 0 1
185 0 1
186 0 1
187 0 1
188 0 1
189 0 1
190 0 1
191 0 1
192 0 1
193 0 1
194 0 1
195 0 1
196 0 1
197 0 1
198 0 1
199 0 1
200 0 1
201 0 1
202 0 1
203 0 1
204 0 1
205 0 1
206 0 1
207 0 1
208 0 1
209 0 1
210 0 1
211 0 1
212 0 1
213 0 1
214 0 1
215 0 1
216 0 1
217 0 1
218 0 1
219 0 1
220 0 1
221 0 1
222 0 1
223 0 1
224 0 1
225 0 1
226 0 1
227 0 1
228 0 1
229 0 1
230 0 1
231 0 1
232 0 1
233 0 1
234 0 1
235 0 1
236 0 1
237 0 1
238 0 1
239 0 1
240 0 1
241 0 1
242 0 1
243 0 1
244 0 1
245 0 1
246 0 1
247 0 1
248 0 1
249 0 1
250 0 1
251 0 1
252 0 1
253 0 1
254 0 1
255 0 1
256 0 1
257 0 1
258 0 1
259 0 1
260 0 1
261 0 1
262 0 1
263 0 1
264 0 1
265 0 1
266 0 1
267 0 1
268 0 1
269 0 1
270 0 1
271 0 1
272 0 1
273 0 1
274 0 1
275 0 1
276 0 1
277 0 1
278 0 1
279 0 1
280 0 1
286 0 182
292 0 1
297 0 1
298 0 1
299 0 1
300 0 1
301 0 1
306 0 1
313 16 182
375 0 1

Cond Coverage for Module : rv_plic
TotalCoveredPercent
Conditions300.00
Logical300.00
Non-Logical00
Event00

 LINE       375
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Toggle Coverage for Module : rv_plic
TotalCoveredPercent
Totals 33 30 90.91
Total Bits 708 688 97.18
Total Bits 0->1 354 344 97.18
Total Bits 1->0 354 344 97.18

Ports 33 30 90.91
Port Bits 708 688 97.18
Port Bits 0->1 354 344 97.18
Port Bits 1->0 354 344 97.18

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_address[27:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_address[29:28] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T5,*T6,*T7 Yes T5,T6,T7 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_i.a_valid Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
tl_o.a_ready Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_error Yes Yes T5,T7,T18 Yes T5,T7,T18 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_sink Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_source[5:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T6,*T7 Yes T5,T6,T7 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
intr_src_i[0] Unreachable Unreachable Unreachable INPUT
intr_src_i[5:1] Yes Yes *T16,*T8,*T9 Yes T16,T8,T9 INPUT
intr_src_i[6] No No No INPUT
intr_src_i[9:7] Yes Yes *T10,*T17,*T13 Yes T10,T17,T13 INPUT
intr_src_i[10] No No No INPUT
intr_src_i[13:11] Yes Yes T8,*T13,*T10 Yes T8,T13,T10 INPUT
intr_src_i[14] No No No INPUT
intr_src_i[27:15] Yes Yes *T8,*T19,*T13 Yes T8,T19,T13 INPUT
intr_src_i[28] No No No INPUT
intr_src_i[66:29] Yes Yes *T8,*T17,*T13 Yes T8,T17,T13 INPUT
intr_src_i[67] No No No INPUT
intr_src_i[81:68] Yes Yes *T10,*T17,*T12 Yes T10,T17,T12 INPUT
intr_src_i[82] No No No INPUT
intr_src_i[97:83] Yes Yes *T8,*T17,*T16 Yes T8,T17,T16 INPUT
intr_src_i[98] No No No INPUT
intr_src_i[167:99] Yes Yes *T4,*T16,*T8 Yes T4,T16,T8 INPUT
intr_src_i[168] No No No INPUT
intr_src_i[181:169] Yes Yes T8,T10,T13 Yes T8,T10,T13 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T16,T8,T9 Yes T16,T8,T9 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT
irq_o Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT
irq_id_o[0][3:0] Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT
irq_id_o[0][4] Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT
irq_id_o[0][5] Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT
irq_id_o[0][6] Yes Yes T8,T20,T21 Yes T8,T20,T21 OUTPUT
irq_id_o[0][7] Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT
msip_o Yes Yes T16,T8,T9 Yes T16,T8,T9 OUTPUT

*Tests covering at least one bit in the range
Branch Coverage for Module : rv_plic
Line No.TotalCoveredPercent
Branches 4 0 0.00
IF 79 2 0 0.00
IF 85 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	79	if (claim_re[i])

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	85	if (complete_we[i])

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Assert Coverage for Module : rv_plic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 8 80.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 8 80.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FpvSecCmBusIntegrity_A 9050556 0 0 0
FpvSecCmRegWeOnehotCheck_A 9050556 0 0 0
Irq0Tied_A 9050556 9048198 0 0
IrqKnownO_A 9050556 9048198 0 0
MsipKnownO_A 9050556 9048198 0 0
TlAReadyKnownO_A 9050556 9048198 0 0
TlDValidKnownO_A 9050556 9048198 0 0
gen_irq_id_known[0].IrqIdKnownO_A 9050556 9048198 0 0
onehot0Claim 9050556 9048198 0 0
onehot0Complete 9050556 9048198 0 0


FpvSecCmBusIntegrity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 0 0 0

Irq0Tied_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 9048198 0 0
T1 113455 113444 0 0
T2 111728 111717 0 0
T3 684913 684793 0 0
T4 147285 147273 0 0
T14 112552 112541 0 0
T22 200018 200006 0 0
T23 121553 121378 0 0
T24 157433 157265 0 0
T25 172741 172566 0 0
T26 164046 163885 0 0

IrqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 9048198 0 0
T1 113455 113444 0 0
T2 111728 111717 0 0
T3 684913 684793 0 0
T4 147285 147273 0 0
T14 112552 112541 0 0
T22 200018 200006 0 0
T23 121553 121378 0 0
T24 157433 157265 0 0
T25 172741 172566 0 0
T26 164046 163885 0 0

MsipKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 9048198 0 0
T1 113455 113444 0 0
T2 111728 111717 0 0
T3 684913 684793 0 0
T4 147285 147273 0 0
T14 112552 112541 0 0
T22 200018 200006 0 0
T23 121553 121378 0 0
T24 157433 157265 0 0
T25 172741 172566 0 0
T26 164046 163885 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 9048198 0 0
T1 113455 113444 0 0
T2 111728 111717 0 0
T3 684913 684793 0 0
T4 147285 147273 0 0
T14 112552 112541 0 0
T22 200018 200006 0 0
T23 121553 121378 0 0
T24 157433 157265 0 0
T25 172741 172566 0 0
T26 164046 163885 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 9048198 0 0
T1 113455 113444 0 0
T2 111728 111717 0 0
T3 684913 684793 0 0
T4 147285 147273 0 0
T14 112552 112541 0 0
T22 200018 200006 0 0
T23 121553 121378 0 0
T24 157433 157265 0 0
T25 172741 172566 0 0
T26 164046 163885 0 0

gen_irq_id_known[0].IrqIdKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 9048198 0 0
T1 113455 113444 0 0
T2 111728 111717 0 0
T3 684913 684793 0 0
T4 147285 147273 0 0
T14 112552 112541 0 0
T22 200018 200006 0 0
T23 121553 121378 0 0
T24 157433 157265 0 0
T25 172741 172566 0 0
T26 164046 163885 0 0

onehot0Claim
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 9048198 0 0
T1 113455 113444 0 0
T2 111728 111717 0 0
T3 684913 684793 0 0
T4 147285 147273 0 0
T14 112552 112541 0 0
T22 200018 200006 0 0
T23 121553 121378 0 0
T24 157433 157265 0 0
T25 172741 172566 0 0
T26 164046 163885 0 0

onehot0Complete
NameAttemptsReal SuccessesFailuresIncomplete
Total 9050556 9048198 0 0
T1 113455 113444 0 0
T2 111728 111717 0 0
T3 684913 684793 0 0
T4 147285 147273 0 0
T14 112552 112541 0 0
T22 200018 200006 0 0
T23 121553 121378 0 0
T24 157433 157265 0 0
T25 172741 172566 0 0
T26 164046 163885 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%