Unified Coverage Report :: Module :: flash_ctrl

Module : flash_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
36.98			36.98

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_flash_ctrl	37.46			37.46

---

Module Instance : tb.dut.top_earlgrey.u_flash_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.46			37.46

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.46			37.46

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : flash_ctrl

	Total	Covered	Percent
Totals	135	103	76.30
Total Bits	2650	980	36.98
Total Bits 0->1	1325	490	36.98
Total Bits 1->0	1325	490	36.98

Ports	135	103	76.30
Port Bits	2650	980	36.98
Port Bits 0->1	1325	490	36.98
Port Bits 1->0	1325	490	36.98

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_iso_part_sw_rd_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_iso_part_sw_wr_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
lc_nvm_debug_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_address[8:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_tl_i.a_address[23:9]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_tl_o.d_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_address[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
prim_tl_i.a_address[14:7]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_address[15]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_address[23:16]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
prim_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
prim_tl_o.d_source[5:0]	Yes	Yes	*T4,*T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mem_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
mem_tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_address[19:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_address[28:20]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_address[29]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_address[31:30]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
otp_o.addr_req	No	No		No		OUTPUT
otp_o.data_req	No	No		No		OUTPUT
otp_i.seed_valid	No	No		No		INPUT
otp_i.rand_key[127:0]	No	No		No		INPUT
otp_i.key[127:0]	No	No		No		INPUT
otp_i.addr_ack	No	No		No		INPUT
otp_i.data_ack	No	No		No		INPUT
rma_req_i[3:0]	No	No		No		INPUT
rma_seed_i[8:0]	No	No		No		INPUT
rma_seed_i[9]	Yes	Yes	*T27	Yes	T27	INPUT
rma_seed_i[13:10]	No	No		No		INPUT
rma_seed_i[18:14]	Yes	Yes	T27	Yes	T27	INPUT
rma_seed_i[21:19]	No	No		No		INPUT
rma_seed_i[24:22]	Yes	Yes	T27	Yes	T27	INPUT
rma_seed_i[29:25]	No	No		No		INPUT
rma_seed_i[31:30]	Yes	Yes	T27	Yes	T27	INPUT
rma_ack_o[3:0]	No	No		No		OUTPUT
pwrmgr_o.flash_idle	No	No		No		OUTPUT
keymgr_o.seeds[1:0][255:0]	No	No		No		OUTPUT
cio_tck_i	Yes	Yes	T28,T23,T24	Yes	T28,T23,T24	INPUT
cio_tms_i	Yes	Yes	T28,T29,T23	Yes	T28,T29,T23	INPUT
cio_tdi_i	Yes	Yes	T28,T30,T23	Yes	T28,T30,T23	INPUT
cio_tdo_en_o	No	No		No		OUTPUT
cio_tdo_o	No	No		No		OUTPUT
intr_corr_err_o	Yes	Yes	T13	Yes	T13	OUTPUT
intr_prog_empty_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
intr_prog_lvl_o	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
intr_rd_full_o	Yes	Yes	T13	Yes	T13	OUTPUT
intr_rd_lvl_o	Yes	Yes	T8,T13,T31	Yes	T8,T13,T31	OUTPUT
intr_op_done_o	Yes	Yes	T8,T10,T17	Yes	T8,T10,T17	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	INPUT
alert_rx_i[2].ping_n	No	No		No		INPUT
alert_rx_i[2].ping_p	No	No		No		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	INPUT
alert_rx_i[3].ping_n	No	No		No		INPUT
alert_rx_i[3].ping_p	No	No		No		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	INPUT
alert_rx_i[4].ping_n	No	No		No		INPUT
alert_rx_i[4].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
fla_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
scan_en_i	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
flash_bist_enable_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
flash_power_down_h_i	No	Yes	T1,T2,T3	No		INPUT
flash_power_ready_h_i	No	No		Yes	T1,T2,T3	INPUT
flash_test_mode_a_io[1:0]	No	No		No		INOUT
flash_test_voltage_h_io	No	No		No		INOUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_flash_ctrl

	Total	Covered	Percent
Totals	128	103	80.47
Total Bits	2616	980	37.46
Total Bits 0->1	1308	490	37.46
Total Bits 1->0	1308	490	37.46

Ports	128	103	80.47
Port Bits	2616	980	37.46
Port Bits 0->1	1308	490	37.46
Port Bits 1->0	1308	490	37.46

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_iso_part_sw_rd_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_iso_part_sw_wr_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
lc_nvm_debug_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_address[8:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_tl_i.a_address[23:9]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
core_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
core_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_tl_o.d_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_address[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
prim_tl_i.a_address[14:7]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_address[15]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_address[23:16]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
prim_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
prim_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
prim_tl_o.d_source[5:0]	Yes	Yes	*T4,*T5,T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mem_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
mem_tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_address[19:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_address[28:20]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_address[29]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_address[31:30]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
mem_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
mem_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
otp_o.addr_req	No	No		No		OUTPUT
otp_o.data_req	No	No		No		OUTPUT
otp_i.seed_valid	No	No		No		INPUT
otp_i.rand_key[127:0]	No	No		No		INPUT
otp_i.key[127:0]	No	No		No		INPUT
otp_i.addr_ack	No	No		No		INPUT
otp_i.data_ack	No	No		No		INPUT
rma_req_i[3:0]	No	No		No		INPUT
rma_seed_i[8:0]	No	No		No		INPUT
rma_seed_i[9]	Yes	Yes	*T27	Yes	T27	INPUT
rma_seed_i[13:10]	No	No		No		INPUT
rma_seed_i[18:14]	Yes	Yes	T27	Yes	T27	INPUT
rma_seed_i[21:19]	No	No		No		INPUT
rma_seed_i[24:22]	Yes	Yes	T27	Yes	T27	INPUT
rma_seed_i[29:25]	No	No		No		INPUT
rma_seed_i[31:30]	Yes	Yes	T27	Yes	T27	INPUT
rma_ack_o[3:0]	No	No		No		OUTPUT
pwrmgr_o.flash_idle	No	No		No		OUTPUT
keymgr_o.seeds[1:0][255:0]	No	No		No		OUTPUT
cio_tck_i	Yes	Yes	T28,T23,T24	Yes	T28,T23,T24	INPUT
cio_tms_i	Yes	Yes	T28,T29,T23	Yes	T28,T29,T23	INPUT
cio_tdi_i	Yes	Yes	T28,T30,T23	Yes	T28,T30,T23	INPUT
cio_tdo_en_o[0:0]	Excluded	Excluded		Excluded		OUTPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
cio_tdo_o[0:0]	Excluded	Excluded		Excluded		OUTPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
intr_corr_err_o	Yes	Yes	T13	Yes	T13	OUTPUT
intr_prog_empty_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
intr_prog_lvl_o	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
intr_rd_full_o	Yes	Yes	T13	Yes	T13	OUTPUT
intr_rd_lvl_o	Yes	Yes	T8,T13,T31	Yes	T8,T13,T31	OUTPUT
intr_op_done_o	Yes	Yes	T8,T10,T17	Yes	T8,T10,T17	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	INPUT
alert_rx_i[2].ping_n	No	No		No		INPUT
alert_rx_i[2].ping_p	No	No		No		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	INPUT
alert_rx_i[3].ping_n	No	No		No		INPUT
alert_rx_i[3].ping_p	No	No		No		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	INPUT
alert_rx_i[4].ping_n	No	No		No		INPUT
alert_rx_i[4].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
obs_ctrl_i.obmen[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obmsl[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obgsl[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
fla_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
scan_en_i	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
flash_bist_enable_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
flash_power_down_h_i	No	Yes	T1,T2,T3	No		INPUT
flash_power_ready_h_i	No	No		Yes	T1,T2,T3	INPUT
flash_test_mode_a_io[1:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_test_voltage_h_io[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.

*Tests covering at least one bit in the range