Unified Coverage Report :: Module :: ibex_top

Module : ibex_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
20.68			20.68

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core	21.20			21.20

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
21.20			21.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
21.20			21.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
57.19	54.12	53.57	62.34		75.00	40.91	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : ibex_top

	Total	Covered	Percent
Totals	40	8	20.00
Total Bits	822	170	20.68
Total Bits 0->1	411	85	20.68
Total Bits 1->0	411	85	20.68

Ports	40	8	20.00
Port Bits	822	170	20.68
Port Bits 0->1	411	85	20.68
Port Bits 1->0	411	85	20.68

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	No	No		No		OUTPUT
instr_gnt_i	No	No		No		INPUT
instr_rvalid_i	No	No		No		INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[31:2]	No	No		No		OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
instr_err_i	No	No		No		INPUT
data_req_o	No	No		No		OUTPUT
data_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_we_o	No	No		No		OUTPUT
data_be_o[3:0]	No	No		No		OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	No	No		No		OUTPUT
data_wdata_o[31:0]	No	No		No		OUTPUT
data_wdata_intg_o[6:0]	No	No		No		OUTPUT
data_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_err_i	No	No		No		INPUT
irq_software_i	No	No		No		INPUT
irq_timer_i	No	No		No		INPUT
irq_external_i	No	No		No		INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	No	No		No		INPUT
scramble_key_valid_i	No	No		No		INPUT
scramble_key_i[127:0]	No	No		No		INPUT
scramble_nonce_i[63:0]	No	No		No		INPUT
scramble_req_o	No	No		No		OUTPUT
debug_req_i	No	No		No		INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	No	No		No		OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_minor_o	No	No		No		OUTPUT
alert_major_internal_o	No	No		No		OUTPUT
alert_major_bus_o	No	No		No		OUTPUT
core_sleep_o	No	No		No		OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

	Total	Covered	Percent
Totals	36	8	22.22
Total Bits	802	170	21.20
Total Bits 0->1	401	85	21.20
Total Bits 1->0	401	85	21.20

Ports	36	8	22.22
Port Bits	802	170	21.20
Port Bits 0->1	401	85	21.20
Port Bits 1->0	401	85	21.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	No	No		No		INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	No	No		No		OUTPUT
instr_gnt_i	No	No		No		INPUT
instr_rvalid_i	No	No		No		INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[31:2]	No	No		No		OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
instr_err_i	No	No		No		INPUT
data_req_o	No	No		No		OUTPUT
data_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_we_o	No	No		No		OUTPUT
data_be_o[3:0]	No	No		No		OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	No	No		No		OUTPUT
data_wdata_o[31:0]	No	No		No		OUTPUT
data_wdata_intg_o[6:0]	No	No		No		OUTPUT
data_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_err_i	No	No		No		INPUT
irq_software_i	No	No		No		INPUT
irq_timer_i	No	No		No		INPUT
irq_external_i	No	No		No		INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	No	No		No		INPUT
scramble_key_valid_i	No	No		No		INPUT
scramble_key_i[127:0]	No	No		No		INPUT
scramble_nonce_i[63:0]	No	No		No		INPUT
scramble_req_o	No	No		No		OUTPUT
debug_req_i	No	No		No		INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	No	No		No		OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_minor_o	No	No		No		OUTPUT
alert_major_internal_o	No	No		No		OUTPUT
alert_major_bus_o	No	No		No		OUTPUT
core_sleep_o	No	No		No		OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT