Unified Coverage Report :: Module :: spi_host

Module : spi_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.50			90.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_host0	91.48			91.48
tb.dut.top_earlgrey.u_spi_host1	92.59			92.59

---

Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.48			91.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.48			91.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59			92.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.59			92.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_host

	Total	Covered	Percent
Totals	46	37	80.43
Total Bits	358	324	90.50
Total Bits 0->1	179	162	90.50
Total Bits 1->0	179	162	90.50

Ports	46	37	80.43
Port Bits	358	324	90.50
Port Bits 0->1	179	162	90.50
Port Bits 1->0	179	162	90.50

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_o.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_sck_o	No	No		No		OUTPUT
cio_sck_en_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_csb_o	No	No		No		OUTPUT
cio_csb_en_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_sd_o[3:0]	No	No		No		OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T8	Yes	T8	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T28,T47,T23	Yes	T28,T47,T23	INPUT
passthrough_i.s_en[3:0]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
passthrough_i.csb_en	No	No		No		INPUT
passthrough_i.csb	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
passthrough_i.sck_en	No	No		No		INPUT
passthrough_i.sck	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
passthrough_i.passthrough_en	Yes	Yes	T8	Yes	T8	INPUT
passthrough_o.s[3:0]	Yes	Yes	T28,T47,T23	Yes	T28,T47,T23	OUTPUT
intr_error_o	Yes	Yes	T8,T13,T17	Yes	T8,T13,T17	OUTPUT
intr_spi_event_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0

	Total	Covered	Percent
Totals	44	37	84.09
Total Bits	352	322	91.48
Total Bits 0->1	176	161	91.48
Total Bits 1->0	176	161	91.48

Ports	44	37	84.09
Port Bits	352	322	91.48
Port Bits 0->1	176	161	91.48
Port Bits 1->0	176	161	91.48

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_o.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_sck_o	No	No		No		OUTPUT
cio_sck_en_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_csb_o	No	No		No		OUTPUT
cio_csb_en_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_sd_o[3:0]	No	No		No		OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T8	Yes	T8	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
passthrough_i.s_en[3:0]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
passthrough_i.csb_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.csb	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
passthrough_i.sck_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.sck	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
passthrough_i.passthrough_en	Yes	Yes	T8	Yes	T8	INPUT
passthrough_o.s[3:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
intr_error_o	Yes	Yes	T8,T12	Yes	T8,T12	OUTPUT
intr_spi_event_o	Yes	Yes	T16,T8,T10	Yes	T16,T8,T10	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1

	Total	Covered	Percent
Totals	38	32	84.21
Total Bits	324	300	92.59
Total Bits 0->1	162	150	92.59
Total Bits 1->0	162	150	92.59

Ports	38	32	84.21
Port Bits	324	300	92.59
Port Bits 0->1	162	150	92.59
Port Bits 1->0	162	150	92.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_o.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
cio_sck_o	No	No		No		OUTPUT
cio_sck_en_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_csb_o	No	No		No		OUTPUT
cio_csb_en_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_sd_o[3:0]	No	No		No		OUTPUT
cio_sd_en_o[3:0]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T28,T47,T23	Yes	T28,T47,T23	INPUT
passthrough_i.s_en[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.s[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.passthrough_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_o.s[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_error_o	Yes	Yes	T8,T13,T17	Yes	T8,T13,T17	OUTPUT
intr_spi_event_o	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	OUTPUT

*Tests covering at least one bit in the range