Unified Coverage Report :: Module :: pinmux_jtag_breakout

Module : pinmux_jtag_breakout

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_jtag_breakout.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_dft_tap_breakout	0.00	0.00		0.00

---

Module Instance : tb.dut.top_earlgrey.u_dft_tap_breakout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pinmux_jtag_breakout

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	17	1	0	0.00
CONT_ASSIGN	18	1	0	0.00
CONT_ASSIGN	19	1	0	0.00
CONT_ASSIGN	20	1	0	0.00
CONT_ASSIGN	21	0	0
CONT_ASSIGN	22	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_jtag_breakout.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_jtag_breakout.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	0	1
18	0	1
19	0	1
20	0	1
21		unreachable
22		unreachable

---

Toggle Coverage for Module : pinmux_jtag_breakout

	Total	Covered	Percent
Totals	10	0	0.00
Total Bits	20	0	0.00
Total Bits 0->1	10	0	0.00
Total Bits 1->0	10	0	0.00

Ports	10	0	0.00
Port Bits	20	0	0.00
Port Bits 0->1	10	0	0.00
Port Bits 1->0	10	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
req_i.tdi	No	No		No		INPUT
req_i.trst_n	No	No		No		INPUT
req_i.tms	No	No		No		INPUT
req_i.tck	No	No		No		INPUT
rsp_o.tdo_oe	No	No		No		OUTPUT
rsp_o.tdo	No	No		No		OUTPUT
tck_o	No	No		No		OUTPUT
trst_no	No	No		No		OUTPUT
tms_o	No	No		No		OUTPUT
tdi_o	No	No		No		OUTPUT
tdo_i	Unreachable	Unreachable		Unreachable		INPUT
tdo_oe_i	Unreachable	Unreachable		Unreachable		INPUT