Unified Coverage Report :: Module :: keymgr

Module : keymgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.05			63.05

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_keymgr	63.05			63.05

---

Module Instance : tb.dut.top_earlgrey.u_keymgr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.05			63.05

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.05			63.05

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : keymgr

	Total	Covered	Percent
Totals	72	47	65.28
Total Bits	10014	6314	63.05
Total Bits 0->1	5007	3157	63.05
Total Bits 1->0	5007	3157	63.05

Ports	72	47	65.28
Port Bits	10014	6314	63.05
Port Bits 0->1	5007	3157	63.05
Port Bits 1->0	5007	3157	63.05

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[7:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[17:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
aes_key_o.key[1:0][255:0]	Yes	Yes	T4,T16,T9	Yes	T4,T16,T9	OUTPUT
aes_key_o.valid	No	No		No		OUTPUT
kmac_key_o.key[1:0][255:0]	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
kmac_key_o.valid	No	No		No		OUTPUT
otbn_key_o.key[1:0][383:0]	Yes	Yes	T4,T16,T9	Yes	T4,T16,T9	OUTPUT
otbn_key_o.valid	No	No		No		OUTPUT
kmac_data_o.last	No	No		No		OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[63:0]	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
kmac_data_o.valid	No	No		No		OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[383:0]	No	No		No		INPUT
kmac_data_i.digest_share0[383:0]	No	No		No		INPUT
kmac_data_i.done	No	No		No		INPUT
kmac_data_i.ready	No	No		No		INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[3:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
lc_keymgr_div_i[4]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[15:5]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[16]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[18:17]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[19]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[35:20]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
lc_keymgr_div_i[36]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[57:37]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[58]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[62:59]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[64:63]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[96:65]	Yes	Yes	*T32,*T35,*T33	Yes	T32,T35,T33	INPUT
lc_keymgr_div_i[97]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[98]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[99]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[127:100]	Yes	Yes	T32,T35,T33	Yes	T32,T35,T33	INPUT
otp_key_i.owner_seed_valid	No	No		No		INPUT
otp_key_i.owner_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_seed_valid	No	No		No		INPUT
otp_key_i.creator_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
otp_device_id_i[255:0]	Yes	Yes	T3,T14,T4	Yes	T3,T14,T4	INPUT
flash_i.seeds[1:0][255:0]	No	No		No		INPUT
edn_o.edn_req	Yes	Yes	T15	Yes	T15	OUTPUT
edn_i.edn_bus[31:0]	No	No		No		INPUT
edn_i.edn_fips	No	No		No		INPUT
edn_i.edn_ack	No	No		No		INPUT
rom_digest_i.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[255:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
intr_op_done_o	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T9,T10,T20	Yes	T9,T10,T20	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T9,T10,T20	Yes	T9,T10,T20	OUTPUT

*Tests covering at least one bit in the range