Unified Coverage Report :: Module Instance :: tb.dut.u_padring.u_prim_mubi4_dec.gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Module Instance : tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic.obs_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							obs_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic.obs_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	15	1	0	0.00
CONT_ASSIGN	16	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	0	1
16	0	1