Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.80 99.93 99.75 99.51 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.80 99.93 99.75 99.51 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL1528152799.93
ALWAYS684375.00
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CONT_ASSIGN1622711100.00
CONT_ASSIGN1624111100.00
CONT_ASSIGN1627511100.00
CONT_ASSIGN1628911100.00
ALWAYS16295199199100.00
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CONT_ASSIGN1732111100.00
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CONT_ASSIGN1732711100.00
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ALWAYS17634199199100.00
ALWAYS17837552552100.00
CONT_ASSIGN1899400
CONT_ASSIGN1900211100.00
CONT_ASSIGN1900311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 0 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16227 1 1
16241 1 1
16275 1 1
16289 1 1
16295 1 1
16296 1 1
16297 1 1
16298 1 1
16299 1 1
16300 1 1
16301 1 1
16302 1 1
16303 1 1
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16305 1 1
16306 1 1
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16308 1 1
16309 1 1
16310 1 1
16311 1 1
16312 1 1
16313 1 1
16314 1 1
16315 1 1
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16317 1 1
16318 1 1
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16327 1 1
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16331 1 1
16332 1 1
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18964 1 1
18968 1 1
18972 1 1
18976 1 1
18980 1 1
18994 unreachable
19002 1 1
19003 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions1983197899.75
Logical1983197899.75
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1648398.97
16484-16500100.00
16500100.00
16500-17011100.00
17014-1762899.72

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 204 203 99.51
TERNARY 16496 2 2 100.00
IF 68 3 2 66.67
CASE 17838 199 199 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16496 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 17838 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T4,T5,T6
addr_hit[1] Covered T16,T37,T8
addr_hit[2] Covered T16,T37,T8
addr_hit[3] Covered T16,T37,T8
addr_hit[4] Covered T16,T37,T8
addr_hit[5] Covered T16,T37,T8
addr_hit[6] Covered T16,T37,T8
addr_hit[7] Covered T16,T37,T8
addr_hit[8] Covered T16,T37,T8
addr_hit[9] Covered T16,T37,T8
addr_hit[10] Covered T16,T37,T8
addr_hit[11] Covered T16,T37,T8
addr_hit[12] Covered T16,T37,T8
addr_hit[13] Covered T16,T37,T8
addr_hit[14] Covered T16,T37,T8
addr_hit[15] Covered T16,T37,T8
addr_hit[16] Covered T16,T37,T8
addr_hit[17] Covered T16,T37,T8
addr_hit[18] Covered T16,T37,T8
addr_hit[19] Covered T16,T37,T8
addr_hit[20] Covered T16,T37,T8
addr_hit[21] Covered T16,T37,T8
addr_hit[22] Covered T16,T37,T8
addr_hit[23] Covered T16,T37,T8
addr_hit[24] Covered T16,T37,T8
addr_hit[25] Covered T16,T37,T8
addr_hit[26] Covered T16,T37,T8
addr_hit[27] Covered T16,T37,T8
addr_hit[28] Covered T16,T37,T8
addr_hit[29] Covered T16,T37,T8
addr_hit[30] Covered T16,T37,T8
addr_hit[31] Covered T16,T37,T8
addr_hit[32] Covered T16,T37,T8
addr_hit[33] Covered T16,T37,T8
addr_hit[34] Covered T16,T37,T8
addr_hit[35] Covered T16,T37,T8
addr_hit[36] Covered T16,T37,T8
addr_hit[37] Covered T16,T37,T8
addr_hit[38] Covered T16,T37,T8
addr_hit[39] Covered T16,T37,T8
addr_hit[40] Covered T16,T37,T8
addr_hit[41] Covered T16,T37,T8
addr_hit[42] Covered T16,T37,T8
addr_hit[43] Covered T16,T37,T8
addr_hit[44] Covered T16,T37,T8
addr_hit[45] Covered T16,T37,T8
addr_hit[46] Covered T16,T37,T8
addr_hit[47] Covered T16,T37,T8
addr_hit[48] Covered T16,T37,T8
addr_hit[49] Covered T16,T37,T8
addr_hit[50] Covered T16,T37,T8
addr_hit[51] Covered T16,T37,T8
addr_hit[52] Covered T16,T37,T8
addr_hit[53] Covered T16,T37,T8
addr_hit[54] Covered T16,T37,T8
addr_hit[55] Covered T16,T37,T8
addr_hit[56] Covered T16,T37,T8
addr_hit[57] Covered T16,T37,T8
addr_hit[58] Covered T16,T37,T8
addr_hit[59] Covered T16,T37,T8
addr_hit[60] Covered T16,T37,T8
addr_hit[61] Covered T16,T37,T8
addr_hit[62] Covered T16,T37,T8
addr_hit[63] Covered T16,T37,T8
addr_hit[64] Covered T16,T37,T8
addr_hit[65] Covered T16,T37,T8
addr_hit[66] Covered T16,T37,T8
addr_hit[67] Covered T16,T37,T8
addr_hit[68] Covered T16,T37,T8
addr_hit[69] Covered T16,T37,T8
addr_hit[70] Covered T16,T37,T8
addr_hit[71] Covered T16,T37,T8
addr_hit[72] Covered T16,T37,T8
addr_hit[73] Covered T16,T37,T8
addr_hit[74] Covered T16,T37,T8
addr_hit[75] Covered T16,T37,T8
addr_hit[76] Covered T16,T37,T8
addr_hit[77] Covered T16,T37,T8
addr_hit[78] Covered T16,T37,T8
addr_hit[79] Covered T16,T37,T8
addr_hit[80] Covered T16,T37,T8
addr_hit[81] Covered T16,T37,T8
addr_hit[82] Covered T16,T37,T8
addr_hit[83] Covered T16,T37,T8
addr_hit[84] Covered T16,T37,T8
addr_hit[85] Covered T16,T37,T8
addr_hit[86] Covered T16,T37,T8
addr_hit[87] Covered T16,T37,T8
addr_hit[88] Covered T16,T37,T8
addr_hit[89] Covered T16,T37,T8
addr_hit[90] Covered T16,T37,T8
addr_hit[91] Covered T16,T37,T8
addr_hit[92] Covered T16,T37,T8
addr_hit[93] Covered T16,T37,T8
addr_hit[94] Covered T16,T37,T8
addr_hit[95] Covered T16,T37,T8
addr_hit[96] Covered T16,T37,T8
addr_hit[97] Covered T16,T37,T8
addr_hit[98] Covered T16,T37,T8
addr_hit[99] Covered T16,T37,T8
addr_hit[100] Covered T16,T37,T8
addr_hit[101] Covered T16,T37,T8
addr_hit[102] Covered T16,T37,T8
addr_hit[103] Covered T16,T37,T8
addr_hit[104] Covered T16,T37,T8
addr_hit[105] Covered T16,T37,T8
addr_hit[106] Covered T16,T37,T8
addr_hit[107] Covered T16,T37,T8
addr_hit[108] Covered T16,T37,T8
addr_hit[109] Covered T16,T37,T8
addr_hit[110] Covered T16,T37,T8
addr_hit[111] Covered T16,T37,T8
addr_hit[112] Covered T16,T37,T8
addr_hit[113] Covered T16,T37,T8
addr_hit[114] Covered T16,T37,T8
addr_hit[115] Covered T16,T37,T8
addr_hit[116] Covered T16,T37,T8
addr_hit[117] Covered T16,T37,T8
addr_hit[118] Covered T16,T37,T8
addr_hit[119] Covered T16,T37,T8
addr_hit[120] Covered T16,T37,T8
addr_hit[121] Covered T16,T37,T8
addr_hit[122] Covered T16,T37,T8
addr_hit[123] Covered T16,T37,T8
addr_hit[124] Covered T16,T37,T8
addr_hit[125] Covered T16,T37,T8
addr_hit[126] Covered T16,T37,T8
addr_hit[127] Covered T16,T37,T8
addr_hit[128] Covered T16,T37,T8
addr_hit[129] Covered T16,T37,T8
addr_hit[130] Covered T16,T37,T8
addr_hit[131] Covered T16,T37,T8
addr_hit[132] Covered T16,T37,T8
addr_hit[133] Covered T16,T37,T8
addr_hit[134] Covered T16,T37,T8
addr_hit[135] Covered T16,T37,T8
addr_hit[136] Covered T16,T37,T8
addr_hit[137] Covered T16,T37,T8
addr_hit[138] Covered T16,T37,T8
addr_hit[139] Covered T16,T37,T8
addr_hit[140] Covered T16,T37,T8
addr_hit[141] Covered T16,T8,T53
addr_hit[142] Covered T16,T37,T8
addr_hit[143] Covered T16,T37,T8
addr_hit[144] Covered T16,T37,T8
addr_hit[145] Covered T16,T37,T8
addr_hit[146] Covered T16,T37,T8
addr_hit[147] Covered T16,T37,T8
addr_hit[148] Covered T16,T37,T8
addr_hit[149] Covered T16,T37,T8
addr_hit[150] Covered T16,T37,T8
addr_hit[151] Covered T16,T37,T8
addr_hit[152] Covered T16,T37,T8
addr_hit[153] Covered T16,T37,T8
addr_hit[154] Covered T16,T37,T8
addr_hit[155] Covered T16,T37,T8
addr_hit[156] Covered T16,T37,T8
addr_hit[157] Covered T16,T37,T8
addr_hit[158] Covered T16,T37,T8
addr_hit[159] Covered T16,T37,T8
addr_hit[160] Covered T16,T37,T8
addr_hit[161] Covered T16,T37,T8
addr_hit[162] Covered T16,T37,T8
addr_hit[163] Covered T16,T37,T8
addr_hit[164] Covered T16,T37,T8
addr_hit[165] Covered T16,T37,T8
addr_hit[166] Covered T16,T37,T8
addr_hit[167] Covered T16,T37,T8
addr_hit[168] Covered T16,T37,T8
addr_hit[169] Covered T16,T37,T8
addr_hit[170] Covered T16,T37,T8
addr_hit[171] Covered T16,T37,T8
addr_hit[172] Covered T16,T37,T8
addr_hit[173] Covered T16,T37,T8
addr_hit[174] Covered T16,T37,T8
addr_hit[175] Covered T16,T37,T8
addr_hit[176] Covered T16,T37,T8
addr_hit[177] Covered T16,T37,T8
addr_hit[178] Covered T16,T37,T8
addr_hit[179] Covered T16,T37,T8
addr_hit[180] Covered T16,T37,T8
addr_hit[181] Covered T16,T37,T8
addr_hit[182] Covered T16,T37,T8
addr_hit[183] Covered T16,T37,T8
addr_hit[184] Covered T16,T37,T8
addr_hit[185] Covered T16,T37,T8
addr_hit[186] Covered T16,T37,T8
addr_hit[187] Covered T16,T37,T8
addr_hit[188] Covered T16,T37,T8
addr_hit[189] Covered T16,T37,T8
addr_hit[190] Covered T16,T37,T8
addr_hit[191] Covered T16,T37,T8
addr_hit[192] Covered T16,T37,T8
addr_hit[193] Covered T16,T37,T8
addr_hit[194] Covered T16,T37,T8
addr_hit[195] Covered T16,T37,T8
addr_hit[196] Covered T16,T37,T8
addr_hit[197] Covered T16,T37,T8
default Covered T5,T6,T7


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 94118529 221177 0 0
reAfterRv 94118529 221177 0 0
rePulse 94118529 179623 0 0
wePulse 94118529 41554 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 94118529 221177 0 0
T8 121041 396 0 0
T9 148176 2213 0 0
T10 114941 396 0 0
T11 359990 1006 0 0
T16 327883 1026 0 0
T20 139892 2309 0 0
T36 354524 954 0 0
T37 225564 99 0 0
T53 98102 40 0 0
T160 130885 87 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 94118529 221177 0 0
T8 121041 396 0 0
T9 148176 2213 0 0
T10 114941 396 0 0
T11 359990 1006 0 0
T16 327883 1026 0 0
T20 139892 2309 0 0
T36 354524 954 0 0
T37 225564 99 0 0
T53 98102 40 0 0
T160 130885 87 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 94118529 179623 0 0
T8 121041 396 0 0
T9 148176 1074 0 0
T10 114941 396 0 0
T11 359990 610 0 0
T13 125572 396 0 0
T16 327883 630 0 0
T20 139892 1145 0 0
T21 131135 1028 0 0
T36 354524 558 0 0
T48 175040 274 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 94118529 41554 0 0
T9 148176 1139 0 0
T11 359990 396 0 0
T16 327883 396 0 0
T20 139892 1164 0 0
T36 354524 396 0 0
T37 225564 99 0 0
T53 98102 40 0 0
T160 130885 87 0 0
T166 202534 160 0 0
T325 39674 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%