Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.69			98.69

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart1	97.37			97.37
tb.dut.top_earlgrey.u_uart0	98.01			98.01
tb.dut.top_earlgrey.u_uart3	98.04			98.04
tb.dut.top_earlgrey.u_uart2	98.68			98.68

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.37			97.37

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.37			97.37

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.01			98.01

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.01			98.01

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04			98.04

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04			98.04

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.68			98.68

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.68			98.68

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	37	94.87
Total Bits	306	302	98.69
Total Bits 0->1	153	151	98.69
Total Bits 1->0	153	151	98.69

Ports	39	37	94.87
Port Bits	306	302	98.69
Port Bits 0->1	153	151	98.69
Port Bits 1->0	153	151	98.69

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_o.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_rx_i	Yes	Yes	T28,T41,T167	Yes	T28,T41,T167	INPUT
cio_tx_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
intr_rx_watermark_o	Yes	Yes	T8,T10,T17	Yes	T8,T10,T17	OUTPUT
intr_tx_empty_o	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	OUTPUT
intr_rx_overflow_o	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T8,T17	Yes	T8,T17	OUTPUT
intr_rx_break_err_o	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	OUTPUT
intr_rx_timeout_o	Yes	Yes	T8,T10,T19	Yes	T8,T10,T19	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	35	89.74
Total Bits	304	296	97.37
Total Bits 0->1	152	148	97.37
Total Bits 1->0	152	148	97.37

Ports	39	35	89.74
Port Bits	304	296	97.37
Port Bits 0->1	152	148	97.37
Port Bits 1->0	152	148	97.37

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T3,*T4,*T22	Yes	T3,T4,T22	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_o.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
cio_rx_i	Yes	Yes	T28,T23,T24	Yes	T28,T23,T24	INPUT
cio_tx_o	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
intr_rx_watermark_o	No	No		No		OUTPUT
intr_tx_empty_o	Yes	Yes	T8,T13	Yes	T8,T13	OUTPUT
intr_rx_overflow_o	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T8	Yes	T8	OUTPUT
intr_rx_break_err_o	No	No		No		OUTPUT
intr_rx_timeout_o	Yes	Yes	T8,T19	Yes	T8,T19	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T13	Yes	T13	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	36	92.31
Total Bits	302	296	98.01
Total Bits 0->1	151	148	98.01
Total Bits 1->0	151	148	98.01

Ports	39	36	92.31
Port Bits	302	296	98.01
Port Bits 0->1	151	148	98.01
Port Bits 1->0	151	148	98.01

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_o.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T8,T10	Yes	T16,T8,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T8,T10	Yes	T16,T8,T10	OUTPUT
cio_rx_i	Yes	Yes	T28,T167,T23	Yes	T28,T167,T23	INPUT
cio_tx_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
intr_rx_watermark_o	Yes	Yes	T10,T12	Yes	T10,T12	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T17	Yes	T13,T17	OUTPUT
intr_rx_overflow_o	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T8	Yes	T8	OUTPUT
intr_rx_break_err_o	No	No		No		OUTPUT
intr_rx_timeout_o	Yes	Yes	T10,T17	Yes	T10,T17	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T13,T17	Yes	T13,T17	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	36	92.31
Total Bits	306	300	98.04
Total Bits 0->1	153	150	98.04
Total Bits 1->0	153	150	98.04

Ports	39	36	92.31
Port Bits	306	300	98.04
Port Bits 0->1	153	150	98.04
Port Bits 1->0	153	150	98.04

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_o.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	OUTPUT
cio_rx_i	Yes	Yes	T28,T168,T23	Yes	T28,T168,T23	INPUT
cio_tx_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
intr_rx_watermark_o	Yes	Yes	T17	Yes	T17	OUTPUT
intr_tx_empty_o	Yes	Yes	T13	Yes	T13	OUTPUT
intr_rx_overflow_o	No	No		No		OUTPUT
intr_rx_frame_err_o	Yes	Yes	T8,T17	Yes	T8,T17	OUTPUT
intr_rx_break_err_o	Yes	Yes	T8,T13	Yes	T8,T13	OUTPUT
intr_rx_timeout_o	Yes	Yes	T10,T12	Yes	T10,T12	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	37	94.87
Total Bits	304	300	98.68
Total Bits 0->1	152	150	98.68
Total Bits 1->0	152	150	98.68

Ports	39	37	94.87
Port Bits	304	300	98.68
Port Bits 0->1	152	150	98.68
Port Bits 1->0	152	150	98.68

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T3,*T4,*T22	Yes	T3,T4,T22	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_o.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	OUTPUT
cio_rx_i	Yes	Yes	T28,T41,T46	Yes	T28,T41,T46	INPUT
cio_tx_o	Yes	Yes	T16,T8,T9	Yes	T16,T8,T9	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T16,T9,T36	Yes	T16,T9,T36	OUTPUT
intr_rx_watermark_o	Yes	Yes	T8,T10,T17	Yes	T8,T10,T17	OUTPUT
intr_tx_empty_o	Yes	Yes	T8,T10	Yes	T8,T10	OUTPUT
intr_rx_overflow_o	Yes	Yes	T8,T10	Yes	T8,T10	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T8,T17	Yes	T8,T17	OUTPUT
intr_rx_break_err_o	Yes	Yes	T8,T10,T17	Yes	T8,T10,T17	OUTPUT
intr_rx_timeout_o	Yes	Yes	T8,T19,T17	Yes	T8,T19,T17	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T8	Yes	T8	OUTPUT

*Tests covering at least one bit in the range