Unified Coverage Report :: Module :: prim_generic_usb_diff_rx

Module : prim_generic_usb_diff_rx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	66.67	33.33			50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic	50.00	66.67	33.33			50.00

---

Module Instance : tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	66.67	33.33			50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
44.44	50.00	33.33			50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_usb_diff_rx

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
obs_buf	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_usb_diff_rx

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	31	1	1	100.00
CONT_ASSIGN	39	1	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv' or '../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26		unreachable
27	1	1
30	1	1
31	1	1
39	0	1
40	0	1
43	1	1

---

Cond Coverage for Module : prim_generic_usb_diff_rx

	Total	Covered	Percent
Conditions	9	3	33.33
Logical	9	3	33.33
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (pullup_p_en_i ? 1'b1 : 1'bz)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       40
 EXPRESSION (pullup_n_en_i ? 1'b1 : 1'bz)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       43
 EXPRESSION (input_en_i ? (input_p & ((~input_n))) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       43
 SUB-EXPRESSION (input_p & ((~input_n)))
                 ---1---   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : prim_generic_usb_diff_rx

	Line No.	Total	Covered	Percent
Branches		6	3	50.00
TERNARY	39	2	1	50.00
TERNARY	40	2	1	50.00
TERNARY	43	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv' or '../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	39	(pullup_p_en_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	40	(pullup_n_en_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	43	(input_en_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3