Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart0_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart0_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart1_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart1_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart2_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart2_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart3_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart3_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c0_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c1_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c2_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T6,T7	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T6,T7	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T6,T7,T18	Yes	T5,T6,T7	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T4,*T5,T6	Yes	T4,T5,T6	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T6,T7	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_pattgen_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T3,*T4,T5	Yes	T3,T4,T5	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T22,*T5,*T6	Yes	T22,T5,T6	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_sink	Yes	Yes	T6,T7,T18	Yes	T6,T7,T18	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T4,*T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_spi_device_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T22,*T5,*T6	Yes	T22,T5,T6	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T22,*T5,*T6	Yes	T22,T5,T6	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T22,T5,T6	Yes	T22,T5,T6	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T3,*T4,*T22	Yes	T3,T4,T22	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T22	Yes	T3,T4,T22	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T3,T4,T22	Yes	T3,T4,T22	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T3,*T4,T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T6,T7,T18	Yes	T5,T6,T7	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T3,*T4,T5	Yes	T3,T4,T5	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T3,*T4,T5	Yes	T3,T4,T5	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T14	Yes	T1,T2,T14	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T14	Yes	T1,T2,T14	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T14	Yes	T1,T2,T14	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T5,T7,T18	Yes	T5,T7,T18	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range