Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.93	96.37	100.00			93.22	94.12	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	16	16	0	0
OutputsKnown_A	1917527	1903063	0	0
gen_no_flops.OutputDelay_A	1917527	1903063	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1917527	1903063	0	0
T1	273576	272646	0	0
T2	269246	268500	0	0
T3	165410	164719	0	0
T4	354663	353838	0	0
T14	271189	270480	0	0
T22	481689	480410	0	0
T23	10317	9214	0	0
T24	9991	9114	0	0
T25	10115	9242	0	0
T26	10243	9354	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1917527	1903063	0	0
T1	273576	272646	0	0
T2	269246	268500	0	0
T3	165410	164719	0	0
T4	354663	353838	0	0
T14	271189	270480	0	0
T22	481689	480410	0	0
T23	10317	9214	0	0
T24	9991	9114	0	0
T25	10115	9242	0	0
T26	10243	9354	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	16	16	0	0
OutputsKnown_A	1917527	1903063	0	0
gen_no_flops.OutputDelay_A	1917527	1903063	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1917527	1903063	0	0
T1	273576	272646	0	0
T2	269246	268500	0	0
T3	165410	164719	0	0
T4	354663	353838	0	0
T14	271189	270480	0	0
T22	481689	480410	0	0
T23	10317	9214	0	0
T24	9991	9114	0	0
T25	10115	9242	0	0
T26	10243	9354	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1917527	1903063	0	0
T1	273576	272646	0	0
T2	269246	268500	0	0
T3	165410	164719	0	0
T4	354663	353838	0	0
T14	271189	270480	0	0
T22	481689	480410	0	0
T23	10317	9214	0	0
T24	9991	9114	0	0
T25	10115	9242	0	0
T26	10243	9354	0	0