Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
26.37			26.37

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_edn0	26.25			26.25
tb.dut.top_earlgrey.u_edn1	41.97			41.97

---

Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
26.25			26.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
26.25			26.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.97			41.97

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.97			41.97

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.22	70.61		85.06			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	78	40	51.28
Total Bits	1206	318	26.37
Total Bits 0->1	603	159	26.37
Total Bits 1->0	603	159	26.37

Ports	78	40	51.28
Port Bits	1206	318	26.37
Port Bits 0->1	603	159	26.37
Port Bits 1->0	603	159	26.37

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i[0].edn_req	Yes	Yes	T15	Yes	T15	INPUT
edn_i[1].edn_req	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[3].edn_req	No	No		No		INPUT
edn_i[4].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[7].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o[0].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[0].edn_fips	No	No		No		OUTPUT
edn_o[0].edn_ack	No	No		No		OUTPUT
edn_o[1].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[1].edn_fips	No	No		No		OUTPUT
edn_o[1].edn_ack	No	No		No		OUTPUT
edn_o[2].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[2].edn_fips	No	No		No		OUTPUT
edn_o[2].edn_ack	No	No		No		OUTPUT
edn_o[3].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[3].edn_fips	No	No		No		OUTPUT
edn_o[3].edn_ack	No	No		No		OUTPUT
edn_o[4].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[4].edn_fips	No	No		No		OUTPUT
edn_o[4].edn_ack	No	No		No		OUTPUT
edn_o[5].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[5].edn_fips	No	No		No		OUTPUT
edn_o[5].edn_ack	No	No		No		OUTPUT
edn_o[6].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[6].edn_fips	No	No		No		OUTPUT
edn_o[6].edn_ack	No	No		No		OUTPUT
edn_o[7].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[7].edn_fips	No	No		No		OUTPUT
edn_o[7].edn_ack	No	No		No		OUTPUT
csrng_cmd_o.genbits_ready	No	No		No		OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	No	No		No		OUTPUT
csrng_cmd_o.csrng_req_valid	No	No		No		OUTPUT
csrng_cmd_i.genbits_bus[127:0]	No	No		No		INPUT
csrng_cmd_i.genbits_fips	No	No		No		INPUT
csrng_cmd_i.genbits_valid	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_sts	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	No	No		No		INPUT
csrng_cmd_i.csrng_req_ready	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T16,T9	Yes	T4,T16,T9	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T16,T9	Yes	T4,T16,T9	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T10,T17	Yes	T10,T17	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T10,T13	Yes	T10,T13	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0

	Total	Covered	Percent
Totals	78	40	51.28
Total Bits	1204	316	26.25
Total Bits 0->1	602	158	26.25
Total Bits 1->0	602	158	26.25

Ports	78	40	51.28
Port Bits	1204	316	26.25
Port Bits 0->1	602	158	26.25
Port Bits 1->0	602	158	26.25

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T4,*T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i[0].edn_req	Yes	Yes	T15	Yes	T15	INPUT
edn_i[1].edn_req	Yes	Yes	T8,T10,T13	Yes	T8,T10,T13	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[3].edn_req	No	No		No		INPUT
edn_i[4].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[7].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_o[0].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[0].edn_fips	No	No		No		OUTPUT
edn_o[0].edn_ack	No	No		No		OUTPUT
edn_o[1].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[1].edn_fips	No	No		No		OUTPUT
edn_o[1].edn_ack	No	No		No		OUTPUT
edn_o[2].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[2].edn_fips	No	No		No		OUTPUT
edn_o[2].edn_ack	No	No		No		OUTPUT
edn_o[3].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[3].edn_fips	No	No		No		OUTPUT
edn_o[3].edn_ack	No	No		No		OUTPUT
edn_o[4].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[4].edn_fips	No	No		No		OUTPUT
edn_o[4].edn_ack	No	No		No		OUTPUT
edn_o[5].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[5].edn_fips	No	No		No		OUTPUT
edn_o[5].edn_ack	No	No		No		OUTPUT
edn_o[6].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[6].edn_fips	No	No		No		OUTPUT
edn_o[6].edn_ack	No	No		No		OUTPUT
edn_o[7].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[7].edn_fips	No	No		No		OUTPUT
edn_o[7].edn_ack	No	No		No		OUTPUT
csrng_cmd_o.genbits_ready	No	No		No		OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	No	No		No		OUTPUT
csrng_cmd_o.csrng_req_valid	No	No		No		OUTPUT
csrng_cmd_i.genbits_bus[127:0]	No	No		No		INPUT
csrng_cmd_i.genbits_fips	No	No		No		INPUT
csrng_cmd_i.genbits_valid	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_sts	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	No	No		No		INPUT
csrng_cmd_i.csrng_req_ready	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T16,T9	Yes	T4,T16,T9	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T16,T9	Yes	T4,T16,T9	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T10	Yes	T10	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T10	Yes	T10	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1

	Total	Covered	Percent
Totals	50	33	66.00
Total Bits	710	298	41.97
Total Bits 0->1	355	149	41.97
Total Bits 1->0	355	149	41.97

Ports	50	33	66.00
Port Bits	710	298	41.97
Port Bits 0->1	355	149	41.97
Port Bits 1->0	355	149	41.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:19]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i[0].edn_req	No	No		No		INPUT
edn_i[1].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[2].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[3].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[4].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[5].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[6].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[7].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_o[0].edn_bus[31:0]	No	No		No		OUTPUT
edn_o[0].edn_fips	No	No		No		OUTPUT
edn_o[0].edn_ack	No	No		No		OUTPUT
edn_o[1].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
csrng_cmd_o.genbits_ready	No	No		No		OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	No	No		No		OUTPUT
csrng_cmd_o.csrng_req_valid	No	No		No		OUTPUT
csrng_cmd_i.genbits_bus[127:0]	No	No		No		INPUT
csrng_cmd_i.genbits_fips	No	No		No		INPUT
csrng_cmd_i.genbits_valid	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_sts	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	No	No		No		INPUT
csrng_cmd_i.csrng_req_ready	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T9,T10	Yes	T16,T9,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T16,T8	Yes	T4,T16,T8	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T17	Yes	T17	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T13	Yes	T13	OUTPUT

*Tests covering at least one bit in the range