Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144418	1			T80	1059		T81	29		T82	107
values[2]	10125	1			T80	173		T81	2		T352	1
values[3]	3631	1			T80	11		T525	5		T678	8
values[4]	1972	1			T525	9		T678	6		T402	3
values[5]	1259	1			T525	4		T678	6		T402	15
values[6]	806	1			T525	8		T678	11		T402	5
values[7]	728	1			T525	6		T678	10		T402	6
values[8]	456	1			T525	4		T678	10		T402	4
values[9]	362	1			T525	6		T678	9		T402	8
values[10]	354	1			T525	10		T678	5		T402	6
values[11]	331	1			T525	5		T678	4		T402	6
values[12]	312	1			T525	4		T678	4		T402	7
values[13]	262	1			T525	9		T678	9		T402	6
values[14]	332	1			T525	9		T678	6		T402	7
values[15]	266	1			T525	4		T678	3		T402	5
values[16]	304	1			T525	8		T678	3		T402	7
values[17]	297	1			T525	12		T678	7		T402	13
values[18]	323	1			T525	7		T678	8		T402	14
values[19]	264	1			T525	4		T678	13		T402	6
values[20]	250	1			T525	3		T678	6		T402	5
values[21]	214	1			T525	2		T678	5		T402	2
values[22]	273	1			T525	6		T678	5		T402	6
values[23]	223	1			T525	14		T678	4		T402	3
values[24]	242	1			T525	12		T678	13		T402	5
values[25]	247	1			T525	5		T678	5		T402	7
values[26]	263	1			T525	3		T678	3		T402	8
values[27]	279	1			T525	11		T678	33		T402	8
values[28]	284	1			T525	2		T678	14		T402	8
values[29]	288	1			T525	8		T678	4		T402	8
values[30]	266	1			T525	16		T678	4		T402	6
values[31]	314	1			T525	17		T678	4		T402	10
values[32]	250	1			T525	12		T678	4		T402	6
values[33]	233	1			T525	3		T678	4		T402	6
values[34]	284	1			T525	5		T678	9		T402	3
values[35]	260	1			T525	4		T678	7		T402	10
values[36]	299	1			T525	4		T678	19		T402	8
values[37]	272	1			T525	7		T678	3		T402	8
values[38]	259	1			T525	5		T678	5		T402	7
values[39]	239	1			T525	3		T678	4		T402	6
values[40]	285	1			T525	3		T678	5		T402	19
values[41]	267	1			T525	6		T678	3		T402	9
values[42]	208	1			T525	12		T678	5		T402	5
values[43]	252	1			T525	17		T678	10		T402	8
values[44]	255	1			T525	18		T678	9		T402	17
values[45]	240	1			T525	9		T678	11		T402	11
values[46]	210	1			T525	5		T678	5		T402	8
values[47]	261	1			T525	4		T678	5		T402	5
values[48]	239	1			T525	3		T678	8		T402	7
values[49]	227	1			T525	4		T678	8		T402	10
values[50]	249	1			T525	13		T678	10		T402	9
values[51]	237	1			T525	3		T678	4		T402	4
values[52]	230	1			T525	7		T678	7		T402	4
values[53]	229	1			T525	2		T678	9		T402	3
values[54]	211	1			T525	7		T678	5		T402	3
values[55]	206	1			T525	4		T678	8		T402	4
values[56]	184	1			T525	8		T678	8		T402	4
values[57]	170	1			T525	8		T678	7		T402	8
values[58]	240	1			T525	11		T678	6		T402	11
values[59]	191	1			T525	5		T678	1		T402	20
values[60]	194	1			T525	10		T402	6		T403	1
values[61]	158	1			T525	15		T402	8		T403	1
values[62]	164	1			T525	29		T402	13		T403	1
values[63]	186	1			T525	7		T402	4		T403	1
values[64]	153	1			T525	5		T402	7		T403	1
values[65]	161	1			T525	6		T402	4		T403	1
values[66]	127	1			T525	6		T402	4		T403	1
values[67]	114	1			T525	11		T402	4		T403	1
values[68]	114	1			T525	2		T402	10		T403	1
values[69]	97	1			T402	8		T403	1		T490	3
values[70]	85	1			T402	5		T403	1		T490	10
values[71]	78	1			T402	5		T403	1		T490	3
values[72]	86	1			T402	5		T403	1		T490	4
values[73]	102	1			T402	14		T403	1		T490	8
values[74]	87	1			T402	10		T403	1		T490	4
values[75]	84	1			T402	1		T403	1		T792	19
values[76]	82	1			T403	1		T792	20		T793	8
values[77]	66	1			T403	1		T792	19		T793	7
values[78]	57	1			T403	1		T792	15		T793	4
values[79]	52	1			T403	1		T792	9		T793	10
values[80]	45	1			T403	1		T792	13		T793	2
values[81]	52	1			T403	1		T792	13		T793	1
values[82]	67	1			T403	1		T792	21		T793	2
values[83]	67	1			T403	1		T792	25		T793	5
values[84]	66	1			T403	1		T792	26		T793	2
values[85]	59	1			T403	6		T792	17		T793	5
values[86]	83	1			T403	4		T792	22		T793	7
values[87]	94	1			T403	5		T792	15		T793	16
values[88]	102	1			T403	3		T792	31		T793	14
values[89]	78	1			T403	1		T792	19		T793	7
values[90]	72	1			T403	3		T792	11		T793	5
values[91]	74	1			T403	13		T792	7		T793	4
values[92]	65	1			T403	3		T792	7		T793	6
values[93]	62	1			T403	3		T792	4		T793	3
values[94]	62	1			T403	2		T792	13		T793	2
values[95]	78	1			T403	5		T792	9		T793	1
values[96]	59	1			T403	1		T792	7		T793	1
values[97]	68	1			T403	4		T792	10		T793	4
values[98]	69	1			T403	3		T792	4		T793	5
values[99]	66	1			T403	5		T792	10		T793	4
values[100]	70	1			T403	2		T792	8		T793	3
values[101]	63	1			T403	2		T792	7		T793	5
values[102]	63	1			T403	2		T792	12		T793	1
values[103]	67	1			T403	2		T792	14		T793	1
values[104]	55	1			T403	3		T792	9		T793	1
values[105]	66	1			T403	2		T792	10		T793	2
values[106]	55	1			T403	3		T792	9		T793	2
values[107]	61	1			T403	2		T792	8		T793	4
values[108]	57	1			T403	4		T792	4		T793	2
values[109]	68	1			T403	2		T792	3		T793	4
values[110]	51	1			T403	1		T792	3		T793	1
values[111]	54	1			T403	2		T792	3		T793	1
values[112]	67	1			T403	2		T792	4		T793	3
values[113]	52	1			T403	1		T792	5		T793	1
values[114]	66	1			T403	2		T792	4		T793	7
values[115]	66	1			T403	1		T792	3		T793	9
values[116]	62	1			T403	3		T792	6		T793	10
values[117]	52	1			T403	1		T792	1		T793	4
values[118]	53	1			T403	2		T792	2		T793	5
values[119]	59	1			T403	1		T792	8		T793	1
values[120]	60	1			T403	2		T792	4		T793	4
values[121]	56	1			T403	1		T792	4		T793	1
values[122]	58	1			T403	1		T792	2		T793	2
values[123]	55	1			T403	2		T792	4		T793	3
values[124]	79	1			T403	2		T792	16		T793	9
values[125]	76	1			T403	6		T792	7		T793	3
values[126]	92	1			T403	4		T792	16		T793	4
values[127]	696	1			T403	35		T792	22		T793	24
values[128]	6407	1			T403	263		T792	12		T793	6

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159167	1			T80	1107		T81	24		T82	86
values[2]	5539	1			T80	67		T81	1		T523	1
values[3]	2612	1			T80	21		T523	2		T492	8
values[4]	1703	1			T80	1		T523	2		T492	8
values[5]	1385	1			T523	3		T492	8		T794	5
values[6]	1139	1			T523	1		T492	10		T794	6
values[7]	897	1			T523	1		T492	4		T794	3
values[8]	751	1			T523	3		T492	7		T794	1
values[9]	677	1			T523	1		T492	12		T794	1
values[10]	608	1			T523	1		T492	11		T794	2
values[11]	558	1			T523	6		T492	6		T794	1
values[12]	492	1			T523	4		T492	2		T794	1
values[13]	451	1			T523	2		T492	10		T794	7
values[14]	426	1			T523	1		T492	25		T794	4
values[15]	356	1			T523	1		T492	16		T794	1
values[16]	347	1			T523	1		T492	20		T794	1
values[17]	375	1			T523	3		T492	28		T794	2
values[18]	355	1			T523	1		T492	7		T794	4
values[19]	355	1			T523	5		T492	19		T794	3
values[20]	389	1			T523	2		T492	49		T794	2
values[21]	368	1			T523	1		T492	42		T794	5
values[22]	292	1			T523	1		T492	30		T794	9
values[23]	274	1			T523	2		T492	32		T794	5
values[24]	278	1			T523	1		T492	36		T794	5
values[25]	267	1			T523	1		T492	27		T794	5
values[26]	303	1			T523	1		T492	38		T794	6
values[27]	256	1			T523	2		T492	10		T794	3
values[28]	173	1			T523	6		T794	3		T795	1
values[29]	165	1			T523	2		T794	3		T795	1
values[30]	134	1			T523	2		T794	5		T795	1
values[31]	169	1			T523	2		T794	2		T795	1
values[32]	166	1			T523	4		T794	2		T795	1
values[33]	158	1			T523	4		T794	4		T795	1
values[34]	163	1			T523	5		T794	2		T795	1
values[35]	140	1			T523	3		T794	4		T795	1
values[36]	122	1			T523	1		T794	6		T795	1
values[37]	110	1			T523	2		T794	2		T795	1
values[38]	98	1			T523	2		T794	2		T795	1
values[39]	106	1			T523	3		T794	1		T795	1
values[40]	106	1			T523	2		T794	1		T795	1
values[41]	91	1			T523	1		T794	2		T795	1
values[42]	80	1			T523	2		T794	1		T795	1
values[43]	82	1			T523	4		T794	3		T795	1
values[44]	103	1			T523	2		T794	6		T795	1
values[45]	124	1			T523	8		T794	1		T795	1
values[46]	106	1			T523	8		T794	2		T795	1
values[47]	116	1			T523	2		T794	3		T795	1
values[48]	116	1			T523	1		T794	6		T795	1
values[49]	102	1			T523	2		T794	4		T795	1
values[50]	109	1			T523	2		T794	5		T795	1
values[51]	70	1			T523	3		T794	2		T795	1
values[52]	59	1			T523	1		T794	2		T795	1
values[53]	69	1			T523	2		T794	2		T795	1
values[54]	63	1			T523	1		T794	8		T795	1
values[55]	68	1			T523	1		T794	6		T795	1
values[56]	70	1			T523	1		T794	7		T795	1
values[57]	58	1			T523	2		T794	2		T795	1
values[58]	42	1			T523	3		T794	1		T795	1
values[59]	58	1			T523	2		T794	1		T795	1
values[60]	65	1			T523	1		T794	2		T795	1
values[61]	78	1			T523	2		T794	6		T795	1
values[62]	53	1			T523	1		T794	2		T795	1
values[63]	57	1			T523	2		T794	3		T795	1
values[64]	59	1			T523	2		T794	3		T795	1
values[65]	62	1			T523	1		T794	4		T795	1
values[66]	50	1			T523	1		T794	1		T795	1
values[67]	61	1			T523	3		T794	1		T795	1
values[68]	62	1			T523	1		T794	2		T795	1
values[69]	47	1			T523	5		T794	3		T795	1
values[70]	54	1			T523	4		T794	1		T795	1
values[71]	59	1			T523	3		T794	1		T795	1
values[72]	49	1			T523	3		T794	3		T795	1
values[73]	51	1			T523	1		T794	4		T795	2
values[74]	58	1			T523	4		T794	3		T795	1
values[75]	45	1			T523	4		T794	2		T795	1
values[76]	53	1			T523	2		T794	2		T795	1
values[77]	67	1			T523	2		T794	7		T795	1
values[78]	57	1			T523	3		T794	11		T795	1
values[79]	60	1			T523	2		T794	2		T795	1
values[80]	70	1			T523	3		T794	3		T795	1
values[81]	51	1			T523	3		T794	2		T795	1
values[82]	66	1			T523	2		T794	5		T795	1
values[83]	66	1			T523	2		T794	1		T795	1
values[84]	57	1			T523	1		T794	4		T795	1
values[85]	66	1			T523	5		T794	1		T795	1
values[86]	71	1			T523	2		T794	3		T795	1
values[87]	60	1			T523	2		T794	2		T795	1
values[88]	61	1			T523	1		T794	2		T795	1
values[89]	74	1			T523	1		T794	3		T795	1
values[90]	67	1			T523	2		T794	4		T795	1
values[91]	79	1			T523	3		T794	1		T795	1
values[92]	74	1			T523	2		T794	2		T795	1
values[93]	59	1			T523	2		T794	1		T795	1
values[94]	70	1			T523	3		T794	3		T795	1
values[95]	75	1			T523	2		T794	8		T795	1
values[96]	71	1			T523	1		T794	7		T795	1
values[97]	73	1			T523	6		T794	10		T795	1
values[98]	100	1			T523	4		T794	7		T795	1
values[99]	73	1			T523	2		T794	5		T795	1
values[100]	69	1			T523	1		T794	4		T795	1
values[101]	79	1			T523	3		T794	2		T795	1
values[102]	78	1			T523	3		T794	2		T795	1
values[103]	83	1			T523	2		T794	8		T795	1
values[104]	80	1			T523	4		T794	6		T795	1
values[105]	80	1			T523	3		T794	4		T795	1
values[106]	106	1			T523	4		T794	8		T795	1
values[107]	83	1			T523	3		T794	8		T795	1
values[108]	89	1			T523	3		T794	4		T795	1
values[109]	97	1			T523	5		T794	4		T795	1
values[110]	89	1			T523	5		T794	9		T795	1
values[111]	89	1			T523	4		T794	4		T795	1
values[112]	92	1			T523	2		T794	5		T795	1
values[113]	112	1			T523	2		T794	2		T795	1
values[114]	118	1			T523	3		T794	3		T795	1
values[115]	103	1			T523	3		T794	3		T795	1
values[116]	99	1			T523	1		T794	1		T795	1
values[117]	94	1			T523	2		T794	7		T795	1
values[118]	99	1			T523	3		T794	8		T795	1
values[119]	106	1			T523	10		T794	8		T795	1
values[120]	118	1			T523	5		T794	7		T795	1
values[121]	121	1			T523	9		T794	6		T795	1
values[122]	111	1			T523	3		T794	2		T795	4
values[123]	158	1			T523	12		T794	4		T795	1
values[124]	293	1			T523	30		T794	17		T795	3
values[125]	566	1			T523	55		T794	20		T795	3
values[126]	1005	1			T523	50		T794	31		T795	23
values[127]	2475	1			T523	14		T794	23		T795	111
values[128]	4180	1			T794	2		T795	190		T796	174

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142022	1			T80	787		T81	30		T82	87
values[2]	10604	1			T80	127		T81	2		T352	82
values[3]	4318	1			T80	84		T352	43		T523	111
values[4]	2500	1			T80	59		T352	18		T523	50
values[5]	1517	1			T80	28		T352	7		T523	19
values[6]	1072	1			T80	20		T352	8		T523	10
values[7]	820	1			T80	20		T352	10		T523	6
values[8]	600	1			T80	8		T352	7		T399	29
values[9]	546	1			T352	11		T399	39		T797	1
values[10]	477	1			T399	18		T797	1		T678	5
values[11]	403	1			T399	7		T797	1		T678	8
values[12]	419	1			T399	3		T797	1		T678	15
values[13]	355	1			T399	3		T797	1		T678	9
values[14]	309	1			T797	1		T678	10		T528	14
values[15]	354	1			T797	2		T678	13		T528	8
values[16]	332	1			T797	1		T678	9		T528	13
values[17]	295	1			T797	1		T678	9		T528	5
values[18]	309	1			T797	1		T678	5		T528	3
values[19]	362	1			T797	1		T678	8		T528	10
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