Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.25	95.38	94.39	95.68		95.08	97.38	99.58

Total tests in report: 2839

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
44.03	44.03	56.41	56.41	49.80	49.80	27.60	27.60			67.61	67.61	62.66	62.66	0.13	0.13	/workspace/coverage/default/0.chip_plic_all_irqs_10.966327992
54.53	10.49	65.47	9.06	60.69	10.89	33.01	5.41			76.67	9.06	90.76	28.10	0.56	0.43	/workspace/coverage/default/2.chip_jtag_csr_rw.537935806
61.52	6.99	75.47	10.00	65.36	4.67	39.47	6.46			77.05	0.38	90.76	0.00	21.02	20.46	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1441462930
65.89	4.36	75.47	0.00	65.37	0.01	39.47	0.00			77.05	0.00	90.76	0.00	47.20	26.18	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3357802633
68.83	2.94	75.47	0.00	65.37	0.00	39.47	0.00			77.05	0.00	90.76	0.00	64.85	17.65	/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.236458799
71.59	2.76	78.98	3.52	72.29	6.92	40.38	0.91			81.73	4.68	90.76	0.00	65.39	0.54	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2270777375
73.92	2.33	84.15	5.16	76.12	3.82	43.85	3.47			83.27	1.53	90.76	0.00	65.39	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3769258035
76.20	2.27	84.15	0.00	76.12	0.00	57.50	13.65			83.27	0.00	90.76	0.00	65.39	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1409766471
78.15	1.95	85.17	1.02	78.38	2.26	62.05	4.55			84.91	1.65	90.76	0.00	67.62	2.23	/workspace/coverage/default/2.chip_sw_alert_test.892832213
79.91	1.76	85.31	0.14	78.50	0.12	71.67	9.62			85.00	0.09	91.13	0.37	67.83	0.21	/workspace/coverage/default/63.chip_sw_all_escalation_resets.2298265950
81.54	1.64	85.31	0.00	78.50	0.00	71.67	0.00			85.00	0.00	91.13	0.00	77.64	9.81	/workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1770797506
82.91	1.37	87.31	2.01	80.54	2.04	73.42	1.75			87.43	2.42	91.13	0.00	77.64	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3884262262
84.21	1.30	87.40	0.09	80.54	0.01	80.94	7.53			87.44	0.01	91.31	0.18	77.64	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1959024586
85.29	1.07	87.40	0.00	81.16	0.62	80.94	0.00			87.69	0.26	91.31	0.00	83.21	5.57	/workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2638955090
86.12	0.83	88.56	1.16	82.91	1.74	81.22	0.27			89.52	1.83	91.31	0.00	83.21	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1804837623
86.91	0.79	88.88	0.32	83.08	0.17	81.24	0.02			89.68	0.16	95.38	4.07	83.21	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1809346264
87.67	0.76	90.34	1.46	83.77	0.69	83.04	1.80			90.11	0.43	95.56	0.18	83.21	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.977021786
88.39	0.72	90.34	0.00	83.77	0.01	83.04	0.00			90.11	0.00	95.56	0.00	87.51	4.30	/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3121789298
89.03	0.64	91.37	1.03	84.61	0.84	83.52	0.48			91.07	0.96	96.12	0.55	87.51	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2321936888
89.63	0.60	91.37	0.00	84.61	0.00	83.52	0.00			91.07	0.00	96.12	0.00	91.11	3.60	/workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1073265622
90.23	0.59	92.08	0.71	85.92	1.31	83.96	0.44			92.17	1.10	96.12	0.00	91.11	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1221105158
90.77	0.55	92.99	0.91	86.86	0.94	84.34	0.37			93.24	1.06	96.12	0.00	91.11	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3176231670
91.28	0.51	92.99	0.00	86.89	0.03	87.36	3.02			93.24	0.00	96.12	0.00	91.11	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.498314357
91.72	0.44	93.00	0.01	89.04	2.15	87.36	0.00			93.24	0.00	96.12	0.00	91.56	0.46	/workspace/coverage/cover_reg_top/3.chip_tl_errors.2632907758
92.13	0.41	93.00	0.00	89.16	0.12	87.36	0.00			93.24	0.01	96.12	0.00	93.89	2.33	/workspace/coverage/cover_reg_top/48.xbar_access_same_device.3084578996
92.44	0.31	93.00	0.01	89.18	0.02	89.04	1.68			93.24	0.00	96.30	0.18	93.89	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1601655428
92.75	0.31	93.00	0.00	89.37	0.19	89.04	0.00			93.30	0.06	96.30	0.00	95.51	1.62	/workspace/coverage/cover_reg_top/16.xbar_stress_all.835634187
92.96	0.21	93.00	0.00	89.38	0.01	89.04	0.00			93.30	0.00	96.30	0.00	96.76	1.25	/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2702190661
93.17	0.21	93.29	0.28	90.05	0.67	89.11	0.08			93.48	0.18	96.30	0.00	96.78	0.02	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3663787716
93.36	0.19	93.29	0.00	90.05	0.00	90.24	1.12			93.48	0.00	96.30	0.00	96.78	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.139981352
93.52	0.16	93.37	0.08	90.14	0.09	91.00	0.76			93.52	0.03	96.30	0.00	96.78	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2413201726
93.67	0.15	93.64	0.27	90.36	0.22	91.12	0.12			93.81	0.30	96.30	0.00	96.78	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.1576584539
93.81	0.14	93.64	0.00	90.60	0.24	91.12	0.00			93.85	0.03	96.30	0.00	97.37	0.59	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1425611248
93.95	0.13	93.64	0.00	90.60	0.00	91.12	0.00			93.85	0.00	96.30	0.00	98.17	0.80	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3739651516
94.06	0.12	93.85	0.22	90.93	0.33	91.29	0.17			93.85	0.00	96.30	0.00	98.17	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1344885600
94.18	0.12	93.85	0.00	90.93	0.00	91.95	0.66			93.85	0.00	96.30	0.00	98.20	0.04	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1076033550
94.29	0.11	93.91	0.05	91.02	0.09	92.42	0.48			93.89	0.05	96.30	0.00	98.20	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1171889428
94.40	0.11	93.91	0.00	91.03	0.01	93.08	0.66			93.89	0.00	96.30	0.00	98.20	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4074876153
94.51	0.11	93.94	0.04	91.31	0.28	93.11	0.03			94.20	0.30	96.30	0.00	98.20	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3860755275
94.60	0.09	93.94	0.00	91.31	0.01	93.65	0.54			94.20	0.00	96.30	0.00	98.20	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2050967333
94.68	0.08	94.09	0.15	91.43	0.12	93.75	0.10			94.32	0.12	96.30	0.00	98.20	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.327133125
94.76	0.08	94.33	0.24	91.55	0.12	93.77	0.02			94.39	0.07	96.30	0.00	98.21	0.01	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290841182
94.84	0.08	94.33	0.00	92.00	0.45	93.77	0.00			94.39	0.00	96.30	0.00	98.21	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.2861741065
94.90	0.06	94.50	0.17	92.13	0.13	93.77	0.00			94.46	0.07	96.30	0.00	98.21	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.41652369
94.96	0.06	94.59	0.09	92.22	0.09	93.89	0.11			94.54	0.07	96.30	0.00	98.21	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1121187912
95.01	0.05	94.60	0.01	92.23	0.01	93.97	0.08			94.56	0.02	96.49	0.18	98.23	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3365389146
95.06	0.05	94.60	0.00	92.37	0.13	93.97	0.00			94.71	0.15	96.49	0.00	98.23	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1747417331
95.11	0.04	94.61	0.01	92.38	0.01	94.02	0.05			94.72	0.01	96.67	0.18	98.24	0.01	/workspace/coverage/default/54.chip_sw_all_escalation_resets.369284624
95.15	0.04	94.64	0.04	92.49	0.10	94.06	0.05			94.78	0.07	96.67	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.312604616
95.19	0.04	94.67	0.03	92.50	0.01	94.06	0.01			94.79	0.01	96.86	0.18	98.25	0.01	/workspace/coverage/default/5.chip_sw_all_escalation_resets.567859187
95.23	0.04	94.67	0.00	92.50	0.00	94.31	0.24			94.79	0.00	96.86	0.00	98.25	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.618193483
95.27	0.04	94.68	0.01	92.52	0.02	94.31	0.00			94.80	0.01	97.04	0.18	98.26	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2359758194
95.31	0.04	94.68	0.01	92.53	0.01	94.31	0.01			94.81	0.01	97.23	0.18	98.27	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.3124133638
95.34	0.04	94.68	0.00	92.65	0.12	94.31	0.00			94.84	0.03	97.23	0.00	98.33	0.06	/workspace/coverage/cover_reg_top/41.xbar_stress_all.80326316
95.37	0.03	94.68	0.00	92.72	0.08	94.31	0.00			94.86	0.02	97.23	0.00	98.44	0.11	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.727509548
95.40	0.03	94.68	0.00	92.72	0.00	94.31	0.00			94.86	0.00	97.41	0.18	98.44	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.689691721
95.43	0.03	94.68	0.00	92.72	0.00	94.49	0.18			94.86	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.206544843
95.46	0.03	94.68	0.00	92.90	0.18	94.49	0.00			94.86	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1673572281
95.49	0.03	94.69	0.01	92.90	0.01	94.65	0.16			94.86	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2195312025
95.52	0.03	94.69	0.00	93.07	0.17	94.65	0.00			94.86	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.2940984593
95.55	0.03	94.69	0.00	93.07	0.00	94.82	0.17			94.86	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3804253785
95.58	0.03	94.71	0.02	93.21	0.13	94.84	0.01			94.86	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.650388845
95.60	0.03	94.78	0.08	93.21	0.00	94.91	0.08			94.87	0.01	97.41	0.00	98.44	0.00	/workspace/coverage/default/3.chip_tap_straps_rma.910996943
95.63	0.03	94.80	0.01	93.35	0.14	94.91	0.00			94.87	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1831269536
95.65	0.02	94.86	0.06	93.38	0.03	94.92	0.01			94.92	0.05	97.41	0.00	98.44	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2211229534
95.67	0.02	94.86	0.00	93.38	0.00	95.04	0.12			94.92	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2104239056
95.69	0.02	94.88	0.02	93.42	0.04	95.08	0.03			94.95	0.03	97.41	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2435678536
95.71	0.02	94.91	0.03	93.47	0.05	95.09	0.01			94.97	0.02	97.41	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3833294498
95.73	0.02	94.91	0.00	93.47	0.00	95.20	0.11			94.97	0.00	97.41	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.248767380
95.75	0.02	94.91	0.00	93.47	0.00	95.20	0.00			94.97	0.00	97.41	0.00	98.54	0.11	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1064316959
95.77	0.02	94.91	0.00	93.56	0.09	95.20	0.00			94.97	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/26.chip_tl_errors.2162564218
95.78	0.01	94.94	0.03	93.58	0.02	95.22	0.03			94.97	0.00	97.41	0.00	98.54	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3681009310
95.79	0.01	94.94	0.00	93.58	0.00	95.22	0.00			94.97	0.00	97.41	0.00	98.61	0.07	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.4235079770
95.80	0.01	94.98	0.04	93.60	0.02	95.22	0.00			94.98	0.01	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.176263005
95.81	0.01	94.98	0.00	93.67	0.06	95.22	0.00			94.98	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/68.xbar_stress_all.1258417779
95.82	0.01	94.98	0.00	93.73	0.06	95.22	0.00			94.98	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2174005446
95.83	0.01	94.98	0.00	93.79	0.06	95.22	0.00			94.98	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_rw.2077578837
95.84	0.01	95.00	0.03	93.80	0.01	95.23	0.01			95.00	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2791764971
95.85	0.01	95.00	0.00	93.85	0.05	95.23	0.00			95.00	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1598069629
95.86	0.01	95.03	0.03	93.86	0.01	95.23	0.01			95.02	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3829709005
95.87	0.01	95.05	0.02	93.87	0.01	95.24	0.01			95.03	0.02	97.41	0.00	98.61	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2899938156
95.88	0.01	95.05	0.00	93.87	0.00	95.29	0.05			95.03	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1317373611
95.89	0.01	95.05	0.01	93.90	0.03	95.31	0.02			95.03	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1941264032
95.89	0.01	95.05	0.00	93.90	0.00	95.35	0.05			95.03	0.00	97.41	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1985920654
95.90	0.01	95.05	0.00	93.90	0.00	95.35	0.00			95.03	0.00	97.41	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.679743681
95.91	0.01	95.05	0.00	93.94	0.05	95.35	0.00			95.03	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1730905031
95.92	0.01	95.05	0.00	93.99	0.04	95.35	0.00			95.03	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/28.xbar_stress_all.1470726463
95.92	0.01	95.05	0.00	94.00	0.01	95.37	0.02			95.03	0.00	97.41	0.00	98.67	0.01	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2164983837
95.93	0.01	95.05	0.00	94.00	0.00	95.41	0.04			95.03	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3902521930
95.94	0.01	95.05	0.00	94.04	0.04	95.41	0.00			95.03	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_gpio.1212034808
95.94	0.01	95.05	0.00	94.06	0.02	95.41	0.00			95.05	0.02	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2507380839
95.95	0.01	95.06	0.01	94.08	0.02	95.42	0.01			95.05	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_pattgen_ios.2116689156
95.95	0.01	95.06	0.00	94.11	0.03	95.42	0.00			95.05	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.1882907612
95.96	0.01	95.06	0.00	94.14	0.03	95.42	0.00			95.05	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/67.xbar_stress_all.4056388619
95.96	0.01	95.06	0.00	94.14	0.01	95.45	0.03			95.05	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2620625471
95.97	0.01	95.06	0.00	94.15	0.01	95.45	0.00			95.05	0.00	97.41	0.00	98.70	0.02	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2258889902
95.98	0.01	95.06	0.00	94.16	0.01	95.45	0.00			95.05	0.00	97.41	0.00	98.72	0.02	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.992368734
95.98	0.01	95.06	0.00	94.16	0.00	95.48	0.03			95.05	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2054329179
95.98	0.01	95.06	0.00	94.16	0.00	95.49	0.02			95.05	0.00	97.41	0.00	98.73	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.1435966394
95.99	0.01	95.06	0.00	94.16	0.00	95.52	0.03			95.05	0.00	97.41	0.00	98.73	0.00	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2276022325
95.99	0.01	95.06	0.00	94.18	0.03	95.52	0.00			95.05	0.00	97.41	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4088816869
96.00	0.01	95.07	0.01	94.19	0.01	95.53	0.01			95.05	0.00	97.41	0.00	98.73	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.636832388
96.00	0.01	95.07	0.00	94.19	0.00	95.53	0.00			95.05	0.00	97.41	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.871732758
96.00	0.01	95.07	0.01	94.21	0.01	95.53	0.01			95.05	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4158491302
96.01	0.01	95.07	0.00	94.23	0.02	95.53	0.00			95.05	0.00	97.41	0.00	98.75	0.00	/workspace/coverage/default/2.chip_sw_gpio.292790417
96.01	0.01	95.07	0.00	94.23	0.01	95.53	0.00			95.06	0.02	97.41	0.00	98.75	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.4173300272
96.01	0.01	95.07	0.00	94.24	0.01	95.53	0.00			95.06	0.00	97.41	0.00	98.77	0.01	/workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.1840624456
96.02	0.01	95.07	0.00	94.24	0.00	95.55	0.02			95.06	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1660180115
96.02	0.01	95.07	0.00	94.26	0.02	95.55	0.00			95.06	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2857323243
96.02	0.01	95.07	0.00	94.28	0.02	95.55	0.00			95.06	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2640378361
96.03	0.01	95.07	0.00	94.28	0.00	95.57	0.02			95.06	0.00	97.41	0.00	98.77	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3179438009
96.03	0.01	95.07	0.00	94.28	0.00	95.57	0.01			95.06	0.00	97.41	0.00	98.78	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3894663349
96.03	0.01	95.07	0.00	94.29	0.01	95.57	0.00			95.06	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.217637572
96.03	0.01	95.07	0.00	94.31	0.01	95.57	0.00			95.06	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/62.xbar_stress_all.3354098206
96.04	0.01	95.07	0.00	94.32	0.01	95.57	0.00			95.06	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3817556112
96.04	0.01	95.07	0.00	94.32	0.00	95.59	0.01			95.06	0.00	97.41	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3024824662
96.04	0.01	95.07	0.00	94.32	0.00	95.59	0.01			95.06	0.00	97.41	0.00	98.79	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2013690043
96.04	0.01	95.07	0.00	94.32	0.00	95.60	0.01			95.06	0.00	97.41	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2047241994
96.05	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2653939642
96.05	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.675401875
96.05	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.83	0.01	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.718988196
96.05	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.84	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.494333246
96.05	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.85	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2120058561
96.06	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.86	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1789592931
96.06	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.87	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1613942646
96.06	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.88	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.653609777
96.06	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.90	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2416451353
96.06	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.91	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3229248487
96.06	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.92	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.4161358670
96.07	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.93	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2032392873
96.07	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.94	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1737535997
96.07	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.95	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3754902396
96.07	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.97	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.202268005
96.07	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.98	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1076431007
96.08	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	98.99	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2936297109
96.08	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.00	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.731727076
96.08	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.01	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1823018926
96.08	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.02	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2628159968
96.08	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.04	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1205621452
96.09	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.05	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3432930679
96.09	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.06	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2792233972
96.09	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.07	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.889653288
96.09	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.08	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2508120716
96.09	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.10	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2923217858
96.10	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.11	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2309347530
96.10	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.12	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.297063343
96.10	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.13	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3442468705
96.10	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.14	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.1935208611
96.10	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.15	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2814528714
96.11	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.17	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1017403215
96.11	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.18	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1813344200
96.11	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.19	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1946674159
96.11	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.20	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.747944239
96.11	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.21	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.1488902496
96.12	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.22	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1751673823
96.12	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.24	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.493797973
96.12	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.25	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.4183212968
96.12	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.26	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.884530945
96.12	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.27	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.486076403
96.13	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.28	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.912951905
96.13	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.30	0.01	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3661138090
96.13	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.31	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.830126765
96.13	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.32	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.515537306
96.13	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.33	0.01	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4217960307
96.14	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.34	0.01	/workspace/coverage/default/49.chip_sw_all_escalation_resets.204020070
96.14	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.35	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.310415538
96.14	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.37	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.2571417331
96.14	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.38	0.01	/workspace/coverage/default/55.chip_sw_all_escalation_resets.3171705770
96.14	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.39	0.01	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3289054479
96.15	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.40	0.01	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2912859399
96.15	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.41	0.01	/workspace/coverage/default/6.chip_sw_all_escalation_resets.569493240
96.15	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.42	0.01	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2002387177
96.15	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.44	0.01	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1055988847
96.15	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.45	0.01	/workspace/coverage/default/66.chip_sw_all_escalation_resets.1362220448
96.15	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.46	0.01	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.416009260
96.16	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.47	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1174738167
96.16	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.48	0.01	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3614514602
96.16	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4246185581
96.16	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227089480
96.16	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1786979180
96.17	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3966223306
96.17	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.942527401
96.17	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3726184797
96.17	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.57	0.01	/workspace/coverage/default/91.chip_sw_all_escalation_resets.112329960
96.17	0.01	95.07	0.00	94.32	0.00	95.60	0.00			95.06	0.00	97.41	0.00	99.58	0.01	/workspace/coverage/default/99.chip_sw_all_escalation_resets.3703873923
96.18	0.01	95.07	0.00	94.33	0.01	95.60	0.00			95.06	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/83.xbar_access_same_device.416460955
96.18	0.01	95.08	0.01	94.33	0.00	95.61	0.01			95.06	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/9.chip_sw_all_escalation_resets.1105588222
96.18	0.01	95.08	0.00	94.33	0.00	95.62	0.01			95.06	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3538586327
96.18	0.01	95.08	0.00	94.33	0.00	95.63	0.01			95.06	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.853767722
96.18	0.01	95.08	0.00	94.33	0.00	95.64	0.01			95.06	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.580194243
96.18	0.01	95.08	0.01	94.33	0.00	95.64	0.01			95.06	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2016384858
96.19	0.01	95.08	0.00	94.33	0.00	95.64	0.00			95.07	0.01	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1494361575
96.19	0.01	95.08	0.00	94.33	0.00	95.64	0.00			95.08	0.01	97.41	0.00	99.58	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.735033018
96.19	0.01	95.08	0.00	94.34	0.01	95.64	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/19.chip_csr_rw.3659000607
96.19	0.01	95.08	0.01	94.34	0.01	95.64	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.192352116
96.19	0.01	95.09	0.01	94.34	0.00	95.64	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1714987223
96.19	0.01	95.09	0.00	94.34	0.00	95.65	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2485361521
96.19	0.01	95.09	0.00	94.34	0.00	95.66	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1556480500
96.19	0.01	95.09	0.00	94.34	0.00	95.66	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.1728152763
96.19	0.01	95.09	0.00	94.34	0.00	95.66	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3247864338
96.20	0.01	95.09	0.00	94.34	0.00	95.67	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2036138192
96.20	0.01	95.09	0.00	94.34	0.00	95.67	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2470877932
96.20	0.01	95.09	0.00	94.35	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.2694869738
96.20	0.01	95.09	0.00	94.35	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1230432911
96.20	0.01	95.09	0.00	94.35	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.290765373
96.20	0.01	95.09	0.00	94.36	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.3628020716
96.20	0.01	95.09	0.00	94.36	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.4084102108
96.20	0.01	95.09	0.00	94.36	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2990335016
96.20	0.01	95.09	0.00	94.37	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3940785515
96.20	0.01	95.09	0.00	94.37	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3401627626
96.20	0.01	95.09	0.00	94.37	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.2890597177
96.20	0.01	95.09	0.00	94.38	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1921663938
96.20	0.01	95.09	0.00	94.38	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/87.xbar_error_random.1765707722
96.20	0.01	95.09	0.00	94.39	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2707067289
96.20	0.01	95.09	0.00	94.39	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3115154270
96.20	0.01	95.09	0.00	94.39	0.01	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.547221889
96.21	0.01	95.09	0.01	94.39	0.00	95.67	0.00			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.130736883
96.21	0.01	95.09	0.00	94.39	0.00	95.68	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4247230430
96.21	0.01	95.09	0.00	94.39	0.00	95.68	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3544199625
96.21	0.01	95.09	0.00	94.39	0.00	95.68	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2051887651
96.21	0.01	95.09	0.00	94.39	0.00	95.68	0.01			95.08	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2925261920

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.137525715
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3425236738
/workspace/coverage/cover_reg_top/0.chip_csr_rw.692532774
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.737886745
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2149128346
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2967874969
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2786176973
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.803136985
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2849401632
/workspace/coverage/cover_reg_top/0.xbar_error_random.1240952192
/workspace/coverage/cover_reg_top/0.xbar_random.3501588005
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1396318961
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.578468969
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2632508044
/workspace/coverage/cover_reg_top/0.xbar_same_source.3126070815
/workspace/coverage/cover_reg_top/0.xbar_smoke.1661341044
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.167669631
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2247123974
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2728645016
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2196093245
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3662098356
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2230980784
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1313346513
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1242847364
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2603718099
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2612729504
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.23376577
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.569308640
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2936157198
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2870118773
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3944669461
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2635212769
/workspace/coverage/cover_reg_top/1.xbar_error_random.179995499
/workspace/coverage/cover_reg_top/1.xbar_random.1209449363
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3295078049
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3748199794
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2595891489
/workspace/coverage/cover_reg_top/1.xbar_same_source.4050384197
/workspace/coverage/cover_reg_top/1.xbar_smoke.3501964142
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.260755224
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3836470
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4098608600
/workspace/coverage/cover_reg_top/1.xbar_stress_all.261788854
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2706975438
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3404402851
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.487468025
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2221351236
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1687412739
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.740867635
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1591659630
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2722770049
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.4153784206
/workspace/coverage/cover_reg_top/10.xbar_error_random.1658947777
/workspace/coverage/cover_reg_top/10.xbar_random.2086506432
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2537504612
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.4154870910
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.122605569
/workspace/coverage/cover_reg_top/10.xbar_same_source.1818010821
/workspace/coverage/cover_reg_top/10.xbar_smoke.2918561932
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1592749413
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3518637525
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3682992331
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1196373391
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3900472542
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3200314430
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3380593203
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.4124232050
/workspace/coverage/cover_reg_top/11.chip_tl_errors.700385179
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1459665749
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1156789738
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4086709779
/workspace/coverage/cover_reg_top/11.xbar_error_random.3487619884
/workspace/coverage/cover_reg_top/11.xbar_random.1419935418
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2205560637
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.572556916
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3164521139
/workspace/coverage/cover_reg_top/11.xbar_same_source.3958679438
/workspace/coverage/cover_reg_top/11.xbar_smoke.847441539
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1615170825
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.719302793
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3623612967
/workspace/coverage/cover_reg_top/11.xbar_stress_all.97402753
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2439888128
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2874717249
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4198195775
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1918197402
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1321294208
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1641324968
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2010388403
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1461471128
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.449649165
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1798764871
/workspace/coverage/cover_reg_top/12.xbar_error_random.332152645
/workspace/coverage/cover_reg_top/12.xbar_random.739472778
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3537852386
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2159492445
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1675227741
/workspace/coverage/cover_reg_top/12.xbar_same_source.3235272360
/workspace/coverage/cover_reg_top/12.xbar_smoke.2287972330
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4289084841
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.371772450
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3873670057
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3420556501
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1520050321
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.877304199
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.478221497
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3949529698
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2001185691
/workspace/coverage/cover_reg_top/13.chip_tl_errors.4055699231
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.797573470
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3322944494
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2469000684
/workspace/coverage/cover_reg_top/13.xbar_error_random.3497055604
/workspace/coverage/cover_reg_top/13.xbar_random.314636715
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3248932367
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.483539872
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1274771936
/workspace/coverage/cover_reg_top/13.xbar_same_source.2340274830
/workspace/coverage/cover_reg_top/13.xbar_smoke.4054689743
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2102118717
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3510863485
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.975114530
/workspace/coverage/cover_reg_top/13.xbar_stress_all.4116014235
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.282002964
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.236585990
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.447357284
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2481094228
/workspace/coverage/cover_reg_top/14.chip_csr_rw.4068237566
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2064633028
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1248517256
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3923935164
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.10618348
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3960141496
/workspace/coverage/cover_reg_top/14.xbar_error_random.3548624934
/workspace/coverage/cover_reg_top/14.xbar_random.3443078619
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3486631987
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.695021905
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2738910098
/workspace/coverage/cover_reg_top/14.xbar_same_source.3182184954
/workspace/coverage/cover_reg_top/14.xbar_smoke.2513934266
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/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1728127814
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3048385556
/workspace/coverage/default/34.chip_sw_all_escalation_resets.897381176
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2392778799
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.63532767
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2920310298
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3106232838
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.304591324
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1252323636
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3869963972
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3274156491
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3955169885
/workspace/coverage/default/4.chip_sw_all_escalation_resets.1305346915
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.851230086
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2472675298
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.778467138
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4231617117
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1236716725
/workspace/coverage/default/4.chip_sw_uart_tx_rx.4033500024
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1906154212
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.729110173
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2937603343
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.201060864
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3490970932
/workspace/coverage/default/4.chip_tap_straps_dev.990367116
/workspace/coverage/default/4.chip_tap_straps_prod.2375272643
/workspace/coverage/default/4.chip_tap_straps_rma.2144051740
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1601068165
/workspace/coverage/default/40.chip_sw_all_escalation_resets.411240544
/workspace/coverage/default/41.chip_sw_all_escalation_resets.669608262
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064817713
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3078019678
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.800677439
/workspace/coverage/default/43.chip_sw_all_escalation_resets.631528444
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.419954162
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2432020145
/workspace/coverage/default/45.chip_sw_all_escalation_resets.648099108
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1754620777
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2965750620
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4225972811
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2338587319
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1427286086
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3793010508
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2711174153
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1577131305
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.974768151
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3137431640
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.15247721
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3158766882
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2796574581
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.472169292
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.779781633
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3349825859
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3725903600
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3556016420
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1477382168
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.756059433
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3060473207
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793845075
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1082495281
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600362853
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3332758940
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.820695544
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1611525352
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2334616791
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2217041703
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2536376892
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3371301904
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3078564589
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3714601061
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3151270997
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3444520369
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.135725211
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1468219955
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1976269481
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3106382074
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2989088422
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3363714945
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1813871725
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2118794432
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1398917267
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1170535548
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3970541805
/workspace/coverage/default/76.chip_sw_all_escalation_resets.4156389585
/workspace/coverage/default/77.chip_sw_all_escalation_resets.559157392
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2284823901
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1783318069
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4220421280
/workspace/coverage/default/8.chip_sw_all_escalation_resets.151651392
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.727334082
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3882096304
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2405039240
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3310799104
/workspace/coverage/default/81.chip_sw_all_escalation_resets.168786919
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2216707533
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2231204411
/workspace/coverage/default/83.chip_sw_all_escalation_resets.469603314
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1208416316
/workspace/coverage/default/84.chip_sw_all_escalation_resets.573270841
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.777991275
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3056555246
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2920045058
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3684168979
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1439499631
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483902439
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3983357060
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3328215057
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2438540435
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2249526311
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3638607965
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.638327119
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1370958797
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3992924851
/workspace/coverage/default/94.chip_sw_all_escalation_resets.4249863915
/workspace/coverage/default/95.chip_sw_all_escalation_resets.433053468
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1953248578
/workspace/coverage/default/97.chip_sw_all_escalation_resets.441793509
/workspace/coverage/default/98.chip_sw_all_escalation_resets.337301093
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1234095380
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2212742183
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.467005778
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1817847526
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4090394684
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.311757209
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1177637034
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1269636596
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2999200124

---

Total test records in report: 2839

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.chip_plic_all_irqs_10.966327992			Apr 16 04:19:44 PM PDT 24	Apr 16 04:28:10 PM PDT 24	4204350488 ps
T2	/workspace/coverage/default/41.chip_sw_all_escalation_resets.669608262			Apr 16 04:50:32 PM PDT 24	Apr 16 05:00:06 PM PDT 24	6353405792 ps
T3	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2849899665			Apr 16 04:22:55 PM PDT 24	Apr 16 04:31:52 PM PDT 24	4969018940 ps
T34	/workspace/coverage/default/63.chip_sw_all_escalation_resets.2298265950			Apr 16 04:50:00 PM PDT 24	Apr 16 04:59:10 PM PDT 24	6131412600 ps
T4	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.183544143			Apr 16 04:16:29 PM PDT 24	Apr 16 05:16:43 PM PDT 24	44330417052 ps
T5	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1171889428			Apr 16 04:22:43 PM PDT 24	Apr 16 08:09:12 PM PDT 24	77542866825 ps
T91	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1601655428			Apr 16 04:36:53 PM PDT 24	Apr 16 04:45:57 PM PDT 24	3487221277 ps
T92	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3189265896			Apr 16 04:19:06 PM PDT 24	Apr 16 04:22:43 PM PDT 24	2579994425 ps
T67	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3284259399			Apr 16 04:38:30 PM PDT 24	Apr 16 04:51:22 PM PDT 24	4925954446 ps
T93	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.998234144			Apr 16 04:30:31 PM PDT 24	Apr 16 04:38:42 PM PDT 24	4691911076 ps
T6	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2164983837			Apr 16 04:16:34 PM PDT 24	Apr 16 07:22:30 PM PDT 24	63147585689 ps
T127	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4249320856			Apr 16 04:18:52 PM PDT 24	Apr 16 04:34:10 PM PDT 24	9738222952 ps
T191	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1941264032			Apr 16 04:45:35 PM PDT 24	Apr 16 05:13:03 PM PDT 24	8109309344 ps
T71	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1476014918			Apr 16 04:24:27 PM PDT 24	Apr 16 05:17:29 PM PDT 24	25994577514 ps
T186	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3365389146			Apr 16 04:49:04 PM PDT 24	Apr 16 04:59:26 PM PDT 24	5033290804 ps
T273	/workspace/coverage/default/77.chip_sw_all_escalation_resets.559157392			Apr 16 04:51:32 PM PDT 24	Apr 16 05:01:39 PM PDT 24	5838699752 ps
T366	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.70168226			Apr 16 04:20:01 PM PDT 24	Apr 16 04:24:11 PM PDT 24	2400586160 ps
T367	/workspace/coverage/default/2.chip_sw_example_manufacturer.340358928			Apr 16 04:32:03 PM PDT 24	Apr 16 04:35:14 PM PDT 24	2248734708 ps
T48	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.977021786			Apr 16 04:26:18 PM PDT 24	Apr 16 05:05:06 PM PDT 24	8623497856 ps
T314	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290841182			Apr 16 04:50:47 PM PDT 24	Apr 16 04:56:20 PM PDT 24	4346313292 ps
T368	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2276022325			Apr 16 04:37:06 PM PDT 24	Apr 16 04:43:43 PM PDT 24	2964781722 ps
T152	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2413201726			Apr 16 04:22:36 PM PDT 24	Apr 16 04:51:02 PM PDT 24	11073796166 ps
T128	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.498314357			Apr 16 04:18:10 PM PDT 24	Apr 16 04:39:36 PM PDT 24	5920269600 ps
T369	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3090017353			Apr 16 04:22:09 PM PDT 24	Apr 16 04:26:36 PM PDT 24	2758561862 ps
T385	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3224330738			Apr 16 04:43:27 PM PDT 24	Apr 16 04:53:14 PM PDT 24	7223026840 ps
T386	/workspace/coverage/default/1.chip_sw_aes_masking_off.3876731981			Apr 16 04:24:54 PM PDT 24	Apr 16 04:29:06 PM PDT 24	3185254029 ps
T160	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3328215057			Apr 16 04:52:43 PM PDT 24	Apr 16 04:58:49 PM PDT 24	4472113632 ps
T387	/workspace/coverage/default/2.chip_sw_hmac_smoketest.2067932408			Apr 16 04:43:20 PM PDT 24	Apr 16 04:49:45 PM PDT 24	3164849426 ps
T51	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3804253785			Apr 16 04:16:57 PM PDT 24	Apr 16 04:21:20 PM PDT 24	3465808963 ps
T311	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.662676239			Apr 16 04:35:08 PM PDT 24	Apr 16 04:43:14 PM PDT 24	5168494648 ps
T52	/workspace/coverage/default/1.chip_tap_straps_rma.1251502362			Apr 16 04:30:04 PM PDT 24	Apr 16 04:44:22 PM PDT 24	8232045691 ps
T49	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2362958872			Apr 16 04:27:00 PM PDT 24	Apr 16 05:25:10 PM PDT 24	12509498136 ps
T864	/workspace/coverage/default/0.chip_sw_example_concurrency.3267820061			Apr 16 04:14:32 PM PDT 24	Apr 16 04:17:31 PM PDT 24	2832279942 ps
T120	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.264557667			Apr 16 04:25:17 PM PDT 24	Apr 16 04:30:31 PM PDT 24	2489927407 ps
T684	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1527904859			Apr 16 04:39:48 PM PDT 24	Apr 16 04:47:48 PM PDT 24	2993092508 ps
T703	/workspace/coverage/default/1.chip_sw_hmac_smoketest.618508431			Apr 16 04:32:46 PM PDT 24	Apr 16 04:39:35 PM PDT 24	3328350680 ps
T194	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1073716873			Apr 16 04:34:57 PM PDT 24	Apr 16 04:49:05 PM PDT 24	5076375048 ps
T198	/workspace/coverage/default/4.chip_sw_uart_tx_rx.4033500024			Apr 16 04:42:58 PM PDT 24	Apr 16 04:54:28 PM PDT 24	4842201724 ps
T685	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.650516923			Apr 16 04:39:53 PM PDT 24	Apr 16 04:55:34 PM PDT 24	7668949224 ps
T849	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2522378241			Apr 16 04:30:12 PM PDT 24	Apr 16 04:39:05 PM PDT 24	5128629640 ps
T436	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1470909450			Apr 16 04:15:19 PM PDT 24	Apr 16 04:22:01 PM PDT 24	7193290104 ps
T54	/workspace/coverage/default/1.chip_tap_straps_dev.335187338			Apr 16 04:30:41 PM PDT 24	Apr 16 04:33:40 PM PDT 24	2363670422 ps
T206	/workspace/coverage/default/93.chip_sw_all_escalation_resets.3992924851			Apr 16 04:56:46 PM PDT 24	Apr 16 05:04:28 PM PDT 24	4714777336 ps
T518	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.419954162			Apr 16 04:48:28 PM PDT 24	Apr 16 04:55:35 PM PDT 24	3684043184 ps
T53	/workspace/coverage/default/2.chip_jtag_csr_rw.537935806			Apr 16 04:31:31 PM PDT 24	Apr 16 05:10:13 PM PDT 24	22091451039 ps
T77	/workspace/coverage/default/0.chip_tap_straps_dev.2877212422			Apr 16 04:18:05 PM PDT 24	Apr 16 04:32:20 PM PDT 24	8561703911 ps
T330	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3894663349			Apr 16 04:49:33 PM PDT 24	Apr 16 04:59:14 PM PDT 24	4871832912 ps
T340	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2814528714			Apr 16 04:46:49 PM PDT 24	Apr 16 04:52:58 PM PDT 24	4234027582 ps
T116	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4247230430			Apr 16 04:21:57 PM PDT 24	Apr 16 05:16:18 PM PDT 24	17949834636 ps
T291	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1477382168			Apr 16 04:49:16 PM PDT 24	Apr 16 04:54:55 PM PDT 24	3843248272 ps
T178	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2422333439			Apr 16 04:25:11 PM PDT 24	Apr 16 04:34:08 PM PDT 24	4171520828 ps
T64	/workspace/coverage/default/2.chip_sw_alert_test.892832213			Apr 16 04:39:21 PM PDT 24	Apr 16 04:44:33 PM PDT 24	2870634036 ps
T336	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2804065559			Apr 16 04:22:36 PM PDT 24	Apr 16 04:28:25 PM PDT 24	3602149390 ps
T341	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3381280346			Apr 16 04:19:20 PM PDT 24	Apr 16 04:25:36 PM PDT 24	3156811150 ps
T669	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1205621452			Apr 16 04:48:28 PM PDT 24	Apr 16 04:54:19 PM PDT 24	4118686400 ps
T426	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1133441205			Apr 16 04:21:59 PM PDT 24	Apr 16 04:43:35 PM PDT 24	7439087577 ps
T865	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1017430005			Apr 16 04:21:15 PM PDT 24	Apr 16 04:26:51 PM PDT 24	2358292672 ps
T233	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.52027850			Apr 16 04:34:05 PM PDT 24	Apr 16 04:47:04 PM PDT 24	5306166936 ps
T691	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1042263686			Apr 16 04:24:47 PM PDT 24	Apr 16 04:29:04 PM PDT 24	3049148982 ps
T50	/workspace/coverage/default/0.rom_e2e_asm_init_prod.289754270			Apr 16 04:25:18 PM PDT 24	Apr 16 05:29:51 PM PDT 24	15010693378 ps
T866	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.993509002			Apr 16 04:34:46 PM PDT 24	Apr 16 04:42:10 PM PDT 24	7365106816 ps
T87	/workspace/coverage/default/54.chip_sw_all_escalation_resets.369284624			Apr 16 04:52:21 PM PDT 24	Apr 16 05:01:13 PM PDT 24	4168523912 ps
T100	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.747944239			Apr 16 04:47:06 PM PDT 24	Apr 16 04:53:59 PM PDT 24	3919257440 ps
T10	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1742023884			Apr 16 04:33:17 PM PDT 24	Apr 16 04:44:47 PM PDT 24	3876136651 ps
T101	/workspace/coverage/default/1.chip_sw_kmac_smoketest.2786415382			Apr 16 04:32:09 PM PDT 24	Apr 16 04:37:18 PM PDT 24	2820434008 ps
T102	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3358055617			Apr 16 04:16:23 PM PDT 24	Apr 16 04:27:51 PM PDT 24	4762543754 ps
T13	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.41652369			Apr 16 04:33:19 PM PDT 24	Apr 16 04:37:47 PM PDT 24	3662031792 ps
T103	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3884258895			Apr 16 04:23:45 PM PDT 24	Apr 16 04:52:35 PM PDT 24	11560532616 ps
T104	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2937603343			Apr 16 04:42:37 PM PDT 24	Apr 16 04:53:37 PM PDT 24	4131061744 ps
T105	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2013690043			Apr 16 04:51:56 PM PDT 24	Apr 16 05:01:49 PM PDT 24	5224974916 ps
T106	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2104239056			Apr 16 04:18:33 PM PDT 24	Apr 16 04:35:23 PM PDT 24	5024983322 ps
T110	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2479275953			Apr 16 04:30:15 PM PDT 24	Apr 16 04:37:01 PM PDT 24	3789290766 ps
T111	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4158344840			Apr 16 04:29:09 PM PDT 24	Apr 16 04:37:27 PM PDT 24	5137020160 ps
T112	/workspace/coverage/default/1.chip_sw_otbn_smoketest.3127215569			Apr 16 04:31:23 PM PDT 24	Apr 16 04:48:12 PM PDT 24	6098479084 ps
T113	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1783318069			Apr 16 04:51:39 PM PDT 24	Apr 16 04:56:22 PM PDT 24	3693428632 ps
T114	/workspace/coverage/default/81.chip_sw_all_escalation_resets.168786919			Apr 16 04:52:45 PM PDT 24	Apr 16 05:02:49 PM PDT 24	4929704472 ps
T406	/workspace/coverage/default/30.chip_sw_all_escalation_resets.1435966394			Apr 16 04:47:58 PM PDT 24	Apr 16 05:00:00 PM PDT 24	4867443600 ps
T175	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1210271676			Apr 16 04:21:20 PM PDT 24	Apr 16 04:24:49 PM PDT 24	2860520199 ps
T245	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.769807961			Apr 16 04:28:43 PM PDT 24	Apr 16 05:19:48 PM PDT 24	13267388512 ps
T283	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1953248578			Apr 16 04:52:32 PM PDT 24	Apr 16 05:04:40 PM PDT 24	4290606286 ps
T284	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1997216789			Apr 16 04:35:12 PM PDT 24	Apr 16 04:53:25 PM PDT 24	5328395254 ps
T192	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3198640028			Apr 16 04:23:32 PM PDT 24	Apr 16 04:34:41 PM PDT 24	4884882872 ps
T285	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.4240495949			Apr 16 04:22:46 PM PDT 24	Apr 16 04:34:30 PM PDT 24	4263015716 ps
T286	/workspace/coverage/default/2.rom_e2e_asm_init_dev.3257084263			Apr 16 04:45:00 PM PDT 24	Apr 16 05:44:01 PM PDT 24	14526262440 ps
T287	/workspace/coverage/default/8.chip_sw_all_escalation_resets.151651392			Apr 16 04:45:35 PM PDT 24	Apr 16 04:55:09 PM PDT 24	5081335500 ps
T288	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2707067289			Apr 16 04:17:45 PM PDT 24	Apr 16 04:30:58 PM PDT 24	4526615160 ps
T289	/workspace/coverage/default/2.chip_sw_kmac_smoketest.2665809253			Apr 16 04:44:30 PM PDT 24	Apr 16 04:51:17 PM PDT 24	3209186778 ps
T657	/workspace/coverage/default/2.chip_sw_edn_sw_mode.529623133			Apr 16 04:37:17 PM PDT 24	Apr 16 05:11:05 PM PDT 24	9877026736 ps
T867	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1533943966			Apr 16 04:20:21 PM PDT 24	Apr 16 04:28:20 PM PDT 24	5219744160 ps
T268	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2472675298			Apr 16 04:44:21 PM PDT 24	Apr 16 04:57:46 PM PDT 24	6054989128 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2349023775			Apr 16 04:40:09 PM PDT 24	Apr 16 05:02:05 PM PDT 24	17882338100 ps
T297	/workspace/coverage/default/2.chip_plic_all_irqs_0.3884262262			Apr 16 04:38:30 PM PDT 24	Apr 16 04:55:39 PM PDT 24	6284854156 ps
T409	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3106232838			Apr 16 04:47:14 PM PDT 24	Apr 16 05:00:09 PM PDT 24	5250805474 ps
T124	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2767610559			Apr 16 04:38:12 PM PDT 24	Apr 16 04:48:27 PM PDT 24	4438728198 ps
T188	/workspace/coverage/default/1.chip_sw_power_idle_load.2195988155			Apr 16 04:31:16 PM PDT 24	Apr 16 04:42:58 PM PDT 24	4208434866 ps
T203	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.800677439			Apr 16 04:51:14 PM PDT 24	Apr 16 04:56:46 PM PDT 24	3264063780 ps
T119	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3295855223			Apr 16 04:40:34 PM PDT 24	Apr 16 05:39:01 PM PDT 24	24883137739 ps
T68	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4074876153			Apr 16 04:21:40 PM PDT 24	Apr 16 05:40:05 PM PDT 24	44178040208 ps
T312	/workspace/coverage/default/66.chip_sw_all_escalation_resets.1362220448			Apr 16 04:51:44 PM PDT 24	Apr 16 05:01:21 PM PDT 24	6187324774 ps
T70	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2737030617			Apr 16 04:16:23 PM PDT 24	Apr 16 04:18:04 PM PDT 24	2417363281 ps
T158	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2920045058			Apr 16 04:52:02 PM PDT 24	Apr 16 04:58:07 PM PDT 24	4076735416 ps
T290	/workspace/coverage/default/83.chip_sw_all_escalation_resets.469603314			Apr 16 04:52:06 PM PDT 24	Apr 16 05:03:57 PM PDT 24	5742486268 ps
T326	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3085526962			Apr 16 04:30:23 PM PDT 24	Apr 16 04:34:45 PM PDT 24	2878151064 ps
T718	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3725903600			Apr 16 04:50:20 PM PDT 24	Apr 16 04:56:58 PM PDT 24	4527227192 ps
T358	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.172912145			Apr 16 04:26:45 PM PDT 24	Apr 16 05:38:53 PM PDT 24	18564758180 ps
T868	/workspace/coverage/default/2.chip_sw_aes_entropy.4120883122			Apr 16 04:37:26 PM PDT 24	Apr 16 04:43:31 PM PDT 24	3278123720 ps
T14	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1095690979			Apr 16 04:22:07 PM PDT 24	Apr 16 04:35:21 PM PDT 24	4085765494 ps
T195	/workspace/coverage/default/2.chip_sw_pattgen_ios.2116689156			Apr 16 04:33:37 PM PDT 24	Apr 16 04:36:45 PM PDT 24	2437848328 ps
T869	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.412342085			Apr 16 04:41:27 PM PDT 24	Apr 16 04:49:06 PM PDT 24	3530325632 ps
T292	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1252323636			Apr 16 04:47:11 PM PDT 24	Apr 16 04:55:02 PM PDT 24	4305067480 ps
T181	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1541370354			Apr 16 04:18:08 PM PDT 24	Apr 16 04:26:17 PM PDT 24	4095253426 ps
T870	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.684905035			Apr 16 04:17:48 PM PDT 24	Apr 16 04:23:49 PM PDT 24	6462841652 ps
T304	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2549064289			Apr 16 04:35:39 PM PDT 24	Apr 16 04:59:19 PM PDT 24	6481397648 ps
T196	/workspace/coverage/default/0.chip_sw_pattgen_ios.426471987			Apr 16 04:16:26 PM PDT 24	Apr 16 04:21:23 PM PDT 24	3603011958 ps
T871	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2350386135			Apr 16 04:34:38 PM PDT 24	Apr 16 04:39:35 PM PDT 24	3049702920 ps
T332	/workspace/coverage/default/89.chip_sw_all_escalation_resets.2438540435			Apr 16 04:52:08 PM PDT 24	Apr 16 05:01:26 PM PDT 24	5812554210 ps
T269	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2939525072			Apr 16 04:16:51 PM PDT 24	Apr 16 04:28:48 PM PDT 24	5379793620 ps
T327	/workspace/coverage/default/0.chip_sw_hmac_enc.1728152763			Apr 16 04:17:09 PM PDT 24	Apr 16 04:20:47 PM PDT 24	2544432464 ps
T328	/workspace/coverage/default/1.chip_sw_hmac_enc.2381579309			Apr 16 04:26:01 PM PDT 24	Apr 16 04:30:42 PM PDT 24	3344489880 ps
T170	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.118923015			Apr 16 04:37:37 PM PDT 24	Apr 16 04:45:58 PM PDT 24	3382720600 ps
T161	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4151588102			Apr 16 04:46:32 PM PDT 24	Apr 16 04:52:52 PM PDT 24	3754781064 ps
T318	/workspace/coverage/default/34.chip_sw_all_escalation_resets.897381176			Apr 16 04:46:26 PM PDT 24	Apr 16 04:54:36 PM PDT 24	5595576168 ps
T872	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.4115383341			Apr 16 04:29:07 PM PDT 24	Apr 16 04:36:34 PM PDT 24	4826706866 ps
T873	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3666182469			Apr 16 04:35:54 PM PDT 24	Apr 16 04:40:52 PM PDT 24	3418495192 ps
T69	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2711174153			Apr 16 04:43:03 PM PDT 24	Apr 16 04:49:13 PM PDT 24	5059114333 ps
T683	/workspace/coverage/default/80.chip_sw_all_escalation_resets.2405039240			Apr 16 04:53:25 PM PDT 24	Apr 16 05:05:08 PM PDT 24	4693738700 ps
T7	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1747417331			Apr 16 04:21:17 PM PDT 24	Apr 16 04:25:29 PM PDT 24	2998458286 ps
T874	/workspace/coverage/default/0.chip_sw_example_manufacturer.2535742882			Apr 16 04:17:44 PM PDT 24	Apr 16 04:21:01 PM PDT 24	2504821928 ps
T199	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.390989580			Apr 16 04:22:32 PM PDT 24	Apr 16 05:13:03 PM PDT 24	13559257692 ps
T122	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1959024586			Apr 16 04:36:28 PM PDT 24	Apr 16 05:12:03 PM PDT 24	23249835256 ps
T123	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1202136776			Apr 16 04:46:30 PM PDT 24	Apr 16 05:01:12 PM PDT 24	14007537059 ps
T659	/workspace/coverage/default/0.chip_sw_edn_kat.3537858283			Apr 16 04:17:54 PM PDT 24	Apr 16 04:28:31 PM PDT 24	3178548726 ps
T319	/workspace/coverage/default/72.chip_sw_all_escalation_resets.3363714945			Apr 16 04:54:06 PM PDT 24	Apr 16 05:02:50 PM PDT 24	4922936742 ps
T270	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2299699924			Apr 16 04:35:50 PM PDT 24	Apr 16 04:45:00 PM PDT 24	3789714960 ps
T121	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1548737242			Apr 16 04:17:57 PM PDT 24	Apr 16 04:27:05 PM PDT 24	5440848136 ps
T174	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2868992326			Apr 16 04:19:15 PM PDT 24	Apr 16 04:30:21 PM PDT 24	4437030338 ps
T875	/workspace/coverage/default/1.rom_e2e_asm_init_dev.2850664069			Apr 16 04:36:55 PM PDT 24	Apr 16 05:38:43 PM PDT 24	14760154614 ps
T876	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2802896791			Apr 16 04:17:15 PM PDT 24	Apr 16 04:28:50 PM PDT 24	4446221340 ps
T169	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2377841218			Apr 16 04:22:34 PM PDT 24	Apr 16 04:47:41 PM PDT 24	9289300746 ps
T877	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3083672243			Apr 16 04:26:13 PM PDT 24	Apr 16 04:29:51 PM PDT 24	2776664052 ps
T320	/workspace/coverage/default/46.chip_sw_all_escalation_resets.2965750620			Apr 16 04:48:03 PM PDT 24	Apr 16 04:58:17 PM PDT 24	4684616944 ps
T45	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3179438009			Apr 16 04:25:27 PM PDT 24	Apr 16 05:28:54 PM PDT 24	18657928194 ps
T65	/workspace/coverage/default/0.chip_sw_alert_test.1541048843			Apr 16 04:20:20 PM PDT 24	Apr 16 04:26:50 PM PDT 24	2978607760 ps
T125	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1102358670			Apr 16 04:39:44 PM PDT 24	Apr 16 04:51:50 PM PDT 24	4878463140 ps
T17	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.882211589			Apr 16 04:21:29 PM PDT 24	Apr 16 04:28:03 PM PDT 24	3660989541 ps
T407	/workspace/coverage/default/2.chip_sw_kmac_app_rom.1595094582			Apr 16 04:37:18 PM PDT 24	Apr 16 04:42:26 PM PDT 24	2945167516 ps
T190	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3282894416			Apr 16 04:25:47 PM PDT 24	Apr 16 04:31:18 PM PDT 24	2771583645 ps
T878	/workspace/coverage/default/1.chip_sw_aes_smoketest.3878731396			Apr 16 04:32:51 PM PDT 24	Apr 16 04:39:15 PM PDT 24	2752569768 ps
T702	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2023454189			Apr 16 04:38:12 PM PDT 24	Apr 16 05:06:46 PM PDT 24	15192435472 ps
T207	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1409766471			Apr 16 04:26:15 PM PDT 24	Apr 16 04:34:00 PM PDT 24	4320770892 ps
T18	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2321936888			Apr 16 04:39:35 PM PDT 24	Apr 16 05:12:02 PM PDT 24	22624959696 ps
T313	/workspace/coverage/default/33.chip_sw_all_escalation_resets.4183212968			Apr 16 04:47:52 PM PDT 24	Apr 16 05:00:54 PM PDT 24	4950453872 ps
T378	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2185138111			Apr 16 04:20:00 PM PDT 24	Apr 16 04:30:26 PM PDT 24	3997839462 ps
T75	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2408501021			Apr 16 04:39:21 PM PDT 24	Apr 16 04:48:28 PM PDT 24	5202818529 ps
T879	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.111684775			Apr 16 04:32:50 PM PDT 24	Apr 16 04:37:36 PM PDT 24	2755689590 ps
T655	/workspace/coverage/default/1.chip_sw_edn_auto_mode.139791213			Apr 16 04:28:31 PM PDT 24	Apr 16 04:44:44 PM PDT 24	3888168612 ps
T165	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.139981352			Apr 16 04:16:18 PM PDT 24	Apr 16 05:56:20 PM PDT 24	46976439348 ps
T300	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3425508710			Apr 16 04:16:34 PM PDT 24	Apr 16 04:26:46 PM PDT 24	4514432346 ps
T94	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2628159968			Apr 16 04:36:33 PM PDT 24	Apr 16 04:42:48 PM PDT 24	3621994080 ps
T168	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1317373611			Apr 16 04:23:02 PM PDT 24	Apr 16 06:04:53 PM PDT 24	50199393894 ps
T200	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1121187912			Apr 16 04:23:05 PM PDT 24	Apr 16 04:54:52 PM PDT 24	13185236986 ps
T880	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.451603761			Apr 16 04:25:12 PM PDT 24	Apr 16 04:34:11 PM PDT 24	6588324094 ps
T881	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2868273959			Apr 16 04:16:07 PM PDT 24	Apr 16 04:24:13 PM PDT 24	4718569736 ps
T76	/workspace/coverage/default/4.chip_tap_straps_rma.2144051740			Apr 16 04:41:50 PM PDT 24	Apr 16 04:44:20 PM PDT 24	2867454246 ps
T379	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1613942646			Apr 16 04:43:57 PM PDT 24	Apr 16 04:54:40 PM PDT 24	6050032260 ps
T15	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3833294498			Apr 16 04:15:20 PM PDT 24	Apr 16 04:48:51 PM PDT 24	8195005178 ps
T882	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1208869373			Apr 16 04:25:32 PM PDT 24	Apr 16 05:15:53 PM PDT 24	12407474550 ps
T521	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2134207296			Apr 16 04:34:09 PM PDT 24	Apr 16 04:59:06 PM PDT 24	13348426906 ps
T690	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.942527401			Apr 16 04:51:44 PM PDT 24	Apr 16 04:58:56 PM PDT 24	3381586512 ps
T296	/workspace/coverage/default/1.chip_plic_all_irqs_0.2174005446			Apr 16 04:28:30 PM PDT 24	Apr 16 04:47:03 PM PDT 24	6230815240 ps
T204	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2113311825			Apr 16 04:16:46 PM PDT 24	Apr 16 04:50:38 PM PDT 24	8006185092 ps
T197	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2755131178			Apr 16 04:21:18 PM PDT 24	Apr 16 07:36:34 PM PDT 24	64598574563 ps
T234	/workspace/coverage/default/75.chip_sw_all_escalation_resets.1170535548			Apr 16 04:51:11 PM PDT 24	Apr 16 04:59:19 PM PDT 24	5920924076 ps
T883	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1528481703			Apr 16 04:21:16 PM PDT 24	Apr 16 04:25:37 PM PDT 24	2668784540 ps
T686	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1047576752			Apr 16 04:46:55 PM PDT 24	Apr 16 04:55:58 PM PDT 24	4345787666 ps
T884	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2336383464			Apr 16 04:17:44 PM PDT 24	Apr 16 04:21:53 PM PDT 24	2791107244 ps
T408	/workspace/coverage/default/0.chip_sw_kmac_app_rom.2955914700			Apr 16 04:19:18 PM PDT 24	Apr 16 04:23:49 PM PDT 24	2841376370 ps
T19	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1405202844			Apr 16 04:32:52 PM PDT 24	Apr 16 04:39:04 PM PDT 24	4680258600 ps
T359	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1094545715			Apr 16 04:25:53 PM PDT 24	Apr 16 05:42:28 PM PDT 24	18969460224 ps
T299	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2122298285			Apr 16 04:42:18 PM PDT 24	Apr 16 04:54:56 PM PDT 24	4152957616 ps
T20	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.327133125			Apr 16 04:35:44 PM PDT 24	Apr 16 05:02:32 PM PDT 24	23170260048 ps
T115	/workspace/coverage/default/1.chip_sw_power_sleep_load.3278036764			Apr 16 04:30:22 PM PDT 24	Apr 16 04:36:32 PM PDT 24	4123286640 ps
T129	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1160810016			Apr 16 04:38:13 PM PDT 24	Apr 16 04:46:17 PM PDT 24	5452994880 ps
T885	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2805541599			Apr 16 04:18:43 PM PDT 24	Apr 16 04:22:45 PM PDT 24	3234380552 ps
T886	/workspace/coverage/default/0.chip_sw_aes_masking_off.1547283926			Apr 16 04:17:55 PM PDT 24	Apr 16 04:24:26 PM PDT 24	2954635102 ps
T236	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1728127814			Apr 16 04:46:37 PM PDT 24	Apr 16 04:52:55 PM PDT 24	3788315720 ps
T277	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.166313826			Apr 16 04:18:03 PM PDT 24	Apr 16 04:36:13 PM PDT 24	10729073393 ps
T278	/workspace/coverage/default/24.chip_sw_all_escalation_resets.966124944			Apr 16 04:46:08 PM PDT 24	Apr 16 04:54:39 PM PDT 24	4365793148 ps
T209	/workspace/coverage/default/90.chip_sw_all_escalation_resets.1370958797			Apr 16 04:53:22 PM PDT 24	Apr 16 05:01:06 PM PDT 24	4152219012 ps
T46	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3365063826			Apr 16 04:25:53 PM PDT 24	Apr 16 05:17:18 PM PDT 24	14582165900 ps
T279	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2146745970			Apr 16 04:41:24 PM PDT 24	Apr 16 04:52:10 PM PDT 24	4624767797 ps
T237	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1976269481			Apr 16 04:51:33 PM PDT 24	Apr 16 04:56:55 PM PDT 24	3454060600 ps
T242	/workspace/coverage/default/0.chip_sw_rv_timer_irq.2398603052			Apr 16 04:18:36 PM PDT 24	Apr 16 04:23:29 PM PDT 24	2920972096 ps
T171	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3650147988			Apr 16 04:15:25 PM PDT 24	Apr 16 04:48:40 PM PDT 24	28742874545 ps
T243	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2402838882			Apr 16 04:34:31 PM PDT 24	Apr 16 04:37:58 PM PDT 24	2063078200 ps
T743	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1823018926			Apr 16 04:46:54 PM PDT 24	Apr 16 04:56:17 PM PDT 24	5937887556 ps
T712	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3048385556			Apr 16 04:46:43 PM PDT 24	Apr 16 04:53:12 PM PDT 24	3914977824 ps
T887	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2597873796			Apr 16 04:40:36 PM PDT 24	Apr 16 04:45:59 PM PDT 24	3467780966 ps
T59	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1282922724			Apr 16 04:18:08 PM PDT 24	Apr 16 04:24:19 PM PDT 24	7757140654 ps
T888	/workspace/coverage/default/2.rom_e2e_asm_init_prod.1013610462			Apr 16 04:43:51 PM PDT 24	Apr 16 05:32:16 PM PDT 24	15733921921 ps
T8	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1804837623			Apr 16 04:16:14 PM PDT 24	Apr 16 04:20:34 PM PDT 24	3217644147 ps
T889	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2025740607			Apr 16 04:37:27 PM PDT 24	Apr 16 04:44:52 PM PDT 24	3871543840 ps
T208	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3327987970			Apr 16 04:17:17 PM PDT 24	Apr 16 04:27:25 PM PDT 24	5079961224 ps
T187	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3191135537			Apr 16 04:16:25 PM PDT 24	Apr 16 08:02:07 PM PDT 24	78042929214 ps
T890	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3252194466			Apr 16 04:40:06 PM PDT 24	Apr 16 04:43:38 PM PDT 24	2023450896 ps
T891	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2842553964			Apr 16 04:35:48 PM PDT 24	Apr 16 04:41:55 PM PDT 24	3460784652 ps
T306	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1577131305			Apr 16 04:43:43 PM PDT 24	Apr 16 04:54:18 PM PDT 24	3867079240 ps
T892	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2036138192			Apr 16 04:17:52 PM PDT 24	Apr 16 04:27:21 PM PDT 24	6141310276 ps
T126	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.199837396			Apr 16 04:28:28 PM PDT 24	Apr 16 04:38:40 PM PDT 24	4320190304 ps
T35	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3681009310			Apr 16 04:33:23 PM PDT 24	Apr 16 04:37:35 PM PDT 24	2755287032 ps
T893	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1069580868			Apr 16 04:39:44 PM PDT 24	Apr 16 04:58:03 PM PDT 24	5504823810 ps
T293	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1052423231			Apr 16 04:26:56 PM PDT 24	Apr 16 04:56:49 PM PDT 24	8628477644 ps
T894	/workspace/coverage/default/0.chip_sw_aes_smoketest.3884545743			Apr 16 04:20:53 PM PDT 24	Apr 16 04:26:16 PM PDT 24	2478927270 ps
T895	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3677455485			Apr 16 04:25:55 PM PDT 24	Apr 16 04:43:38 PM PDT 24	10463752060 ps
T711	/workspace/coverage/default/0.chip_tap_straps_prod.1537976170			Apr 16 04:17:01 PM PDT 24	Apr 16 04:52:47 PM PDT 24	17038922145 ps
T337	/workspace/coverage/default/1.chip_sival_flash_info_access.920042605			Apr 16 04:23:00 PM PDT 24	Apr 16 04:27:13 PM PDT 24	2586713878 ps
T162	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1660180115			Apr 16 04:17:44 PM PDT 24	Apr 16 04:19:30 PM PDT 24	2487406707 ps
T130	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1455594052			Apr 16 04:37:29 PM PDT 24	Apr 16 04:44:54 PM PDT 24	5459604342 ps
T896	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1906154212			Apr 16 04:43:45 PM PDT 24	Apr 16 04:55:06 PM PDT 24	4923226311 ps
T346	/workspace/coverage/default/2.chip_sw_edn_boot_mode.479447162			Apr 16 04:36:44 PM PDT 24	Apr 16 04:45:02 PM PDT 24	3319580786 ps
T897	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2549666031			Apr 16 04:18:14 PM PDT 24	Apr 16 05:02:56 PM PDT 24	12929067688 ps
T756	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1468219955			Apr 16 04:51:19 PM PDT 24	Apr 16 04:57:09 PM PDT 24	3950228972 ps
T255	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4162615565			Apr 16 04:39:15 PM PDT 24	Apr 16 04:48:53 PM PDT 24	8822340663 ps
T898	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.857985962			Apr 16 04:42:20 PM PDT 24	Apr 16 04:54:14 PM PDT 24	4471756932 ps
T899	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3310799104			Apr 16 04:51:28 PM PDT 24	Apr 16 04:57:46 PM PDT 24	3910070504 ps
T176	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2742697576			Apr 16 04:29:27 PM PDT 24	Apr 16 04:34:08 PM PDT 24	2746598221 ps
T72	/workspace/coverage/default/3.chip_tap_straps_rma.910996943			Apr 16 04:41:45 PM PDT 24	Apr 16 04:57:37 PM PDT 24	8668179323 ps
T900	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3175241693			Apr 16 04:26:49 PM PDT 24	Apr 16 05:15:38 PM PDT 24	12210653040 ps
T107	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3272723822			Apr 16 04:19:47 PM PDT 24	Apr 16 04:57:16 PM PDT 24	20527158040 ps
T682	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3137431640			Apr 16 04:50:46 PM PDT 24	Apr 16 04:57:29 PM PDT 24	3876984800 ps
T788	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3151270997			Apr 16 04:45:10 PM PDT 24	Apr 16 04:53:35 PM PDT 24	4481536352 ps
T901	/workspace/coverage/default/2.rom_e2e_asm_init_rma.1180902435			Apr 16 04:46:33 PM PDT 24	Apr 16 05:34:23 PM PDT 24	15479277425 ps
T271	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2094758903			Apr 16 04:17:31 PM PDT 24	Apr 16 04:23:52 PM PDT 24	3277200900 ps
T752	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.667248475			Apr 16 04:50:32 PM PDT 24	Apr 16 04:57:27 PM PDT 24	4109957840 ps
T227	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.618193483			Apr 16 04:34:22 PM PDT 24	Apr 16 04:41:54 PM PDT 24	5586365076 ps
T902	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.532543488			Apr 16 04:38:16 PM PDT 24	Apr 16 04:49:40 PM PDT 24	5122595308 ps
T903	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1909089021			Apr 16 04:37:37 PM PDT 24	Apr 16 04:48:34 PM PDT 24	4102223020 ps
T235	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3726184797			Apr 16 04:51:45 PM PDT 24	Apr 16 05:00:26 PM PDT 24	3942606872 ps
T904	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3812149489			Apr 16 04:36:43 PM PDT 24	Apr 16 04:40:42 PM PDT 24	3280071112 ps
T39	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3889958620			Apr 16 04:35:16 PM PDT 24	Apr 16 04:41:41 PM PDT 24	4212287252 ps
T905	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3305401828			Apr 16 04:45:34 PM PDT 24	Apr 16 04:48:53 PM PDT 24	2066798500 ps
T251	/workspace/coverage/default/1.rom_volatile_raw_unlock.2076067460			Apr 16 04:31:41 PM PDT 24	Apr 16 04:33:31 PM PDT 24	2888558034 ps
T906	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.4083283170			Apr 16 04:35:14 PM PDT 24	Apr 16 04:51:58 PM PDT 24	10582063734 ps
T907	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.4291063152			Apr 16 04:28:20 PM PDT 24	Apr 16 04:39:06 PM PDT 24	7911813656 ps
T83	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3060719384			Apr 16 04:29:45 PM PDT 24	Apr 16 04:35:12 PM PDT 24	3529500050 ps
T193	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1752439982			Apr 16 04:16:24 PM PDT 24	Apr 16 04:21:10 PM PDT 24	3224095137 ps
T689	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1439499631			Apr 16 04:52:32 PM PDT 24	Apr 16 04:58:42 PM PDT 24	3617814384 ps
T256	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3754317097			Apr 16 04:27:20 PM PDT 24	Apr 16 04:35:31 PM PDT 24	9476975703 ps
T11	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.312604616			Apr 16 04:22:46 PM PDT 24	Apr 16 04:31:28 PM PDT 24	4775053173 ps
T757	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3229248487			Apr 16 04:50:34 PM PDT 24	Apr 16 04:58:34 PM PDT 24	3578427064 ps