Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159018	1			T80	621		T81	25		T82	97
values[2]	4387	1			T80	7		T81	4		T239	1
values[3]	2107	1			T399	63		T396	1		T807	1
values[4]	1504	1			T399	59		T396	1		T807	1
values[5]	1172	1			T399	37		T396	1		T807	1
values[6]	912	1			T399	37		T396	1		T807	1
values[7]	862	1			T399	41		T396	1		T807	1
values[8]	732	1			T399	15		T396	1		T807	1
values[9]	676	1			T399	15		T396	1		T807	1
values[10]	717	1			T399	14		T396	1		T807	1
values[11]	685	1			T399	12		T396	1		T807	1
values[12]	559	1			T399	22		T396	1		T807	1
values[13]	487	1			T399	10		T396	1		T807	1
values[14]	409	1			T399	5		T396	1		T807	1
values[15]	376	1			T399	4		T396	1		T807	1
values[16]	329	1			T399	2		T396	1		T807	1
values[17]	290	1			T396	1		T807	1		T796	1
values[18]	247	1			T396	1		T807	1		T796	1
values[19]	231	1			T396	1		T807	1		T796	1
values[20]	255	1			T396	1		T807	1		T796	1
values[21]	205	1			T396	1		T807	1		T796	1
values[22]	169	1			T396	1		T807	1		T796	1
values[23]	168	1			T396	1		T807	1		T796	1
values[24]	163	1			T396	1		T807	1		T796	1
values[25]	158	1			T396	1		T807	1		T796	1
values[26]	170	1			T396	1		T807	1		T796	1
values[27]	170	1			T396	1		T807	1		T796	1
values[28]	131	1			T396	1		T807	1		T796	1
values[29]	140	1			T396	1		T807	1		T796	1
values[30]	143	1			T396	1		T807	1		T796	1
values[31]	120	1			T396	1		T807	1		T796	1
values[32]	160	1			T396	1		T807	1		T796	1
values[33]	155	1			T396	1		T807	1		T796	1
values[34]	130	1			T396	2		T807	1		T796	1
values[35]	118	1			T396	1		T807	1		T796	1
values[36]	99	1			T396	1		T807	1		T796	1
values[37]	87	1			T396	1		T807	1		T796	1
values[38]	87	1			T396	1		T807	1		T796	1
values[39]	92	1			T396	1		T807	1		T796	1
values[40]	88	1			T396	1		T807	1		T796	1
values[41]	75	1			T396	1		T807	1		T796	1
values[42]	62	1			T396	1		T807	1		T796	1
values[43]	58	1			T396	1		T807	1		T796	1
values[44]	56	1			T396	1		T807	1		T796	1
values[45]	65	1			T396	1		T807	1		T796	1
values[46]	60	1			T396	1		T807	1		T796	1
values[47]	55	1			T396	1		T807	1		T796	1
values[48]	76	1			T396	1		T807	1		T796	1
values[49]	71	1			T396	1		T807	1		T796	1
values[50]	65	1			T396	1		T807	1		T796	1
values[51]	53	1			T396	1		T807	1		T796	1
values[52]	61	1			T396	1		T807	1		T796	1
values[53]	56	1			T396	1		T807	1		T796	1
values[54]	63	1			T396	1		T807	1		T796	1
values[55]	59	1			T396	1		T807	1		T796	1
values[56]	53	1			T396	1		T807	1		T796	1
values[57]	58	1			T396	1		T807	1		T796	1
values[58]	74	1			T396	1		T807	1		T796	2
values[59]	68	1			T396	2		T807	1		T796	1
values[60]	64	1			T396	1		T807	1		T796	1
values[61]	68	1			T396	1		T807	1		T796	1
values[62]	67	1			T396	1		T807	1		T796	1
values[63]	52	1			T396	1		T807	1		T796	1
values[64]	54	1			T396	1		T807	1		T796	1
values[65]	67	1			T396	1		T807	1		T796	1
values[66]	60	1			T396	1		T807	1		T796	1
values[67]	57	1			T396	1		T807	1		T796	1
values[68]	60	1			T396	1		T807	1		T796	1
values[69]	74	1			T396	1		T807	1		T796	1
values[70]	64	1			T396	1		T807	1		T796	1
values[71]	66	1			T396	2		T807	1		T796	1
values[72]	59	1			T396	1		T807	1		T796	1
values[73]	58	1			T396	1		T807	1		T796	1
values[74]	56	1			T396	1		T807	1		T796	1
values[75]	66	1			T396	1		T807	1		T796	1
values[76]	65	1			T396	1		T807	1		T796	1
values[77]	70	1			T396	2		T807	1		T796	1
values[78]	69	1			T396	1		T807	1		T796	1
values[79]	66	1			T396	1		T807	1		T796	1
values[80]	73	1			T396	1		T807	1		T796	1
values[81]	71	1			T396	1		T807	1		T796	1
values[82]	72	1			T396	1		T807	1		T796	1
values[83]	76	1			T396	1		T807	1		T796	1
values[84]	82	1			T396	1		T807	1		T796	1
values[85]	74	1			T396	1		T807	2		T796	1
values[86]	66	1			T396	1		T807	1		T796	1
values[87]	75	1			T396	1		T807	1		T796	1
values[88]	79	1			T396	1		T807	1		T796	1
values[89]	92	1			T396	1		T807	1		T796	1
values[90]	70	1			T396	1		T807	1		T796	1
values[91]	74	1			T396	2		T807	1		T796	1
values[92]	92	1			T396	5		T807	1		T796	1
values[93]	88	1			T396	4		T807	1		T796	1
values[94]	99	1			T396	8		T807	1		T796	1
values[95]	88	1			T396	6		T807	1		T796	1
values[96]	91	1			T396	3		T807	1		T796	1
values[97]	92	1			T396	6		T807	1		T796	1
values[98]	80	1			T396	3		T807	1		T796	1
values[99]	88	1			T396	3		T807	1		T796	1
values[100]	96	1			T396	9		T807	1		T796	2
values[101]	89	1			T396	4		T807	1		T796	1
values[102]	90	1			T396	3		T807	1		T796	1
values[103]	84	1			T396	1		T807	1		T796	1
values[104]	92	1			T396	4		T807	1		T796	1
values[105]	94	1			T396	6		T807	1		T796	1
values[106]	107	1			T396	2		T807	1		T796	1
values[107]	91	1			T396	1		T807	1		T796	1
values[108]	92	1			T396	1		T807	1		T796	1
values[109]	97	1			T396	1		T807	2		T796	1
values[110]	104	1			T396	3		T807	3		T796	1
values[111]	115	1			T396	3		T807	7		T796	1
values[112]	106	1			T396	2		T807	4		T796	1
values[113]	118	1			T396	3		T807	1		T796	1
values[114]	123	1			T396	3		T807	1		T796	1
values[115]	145	1			T396	2		T807	4		T796	1
values[116]	150	1			T396	1		T807	2		T796	1
values[117]	122	1			T396	1		T807	1		T796	1
values[118]	115	1			T396	1		T807	1		T796	1
values[119]	106	1			T396	2		T807	1		T796	1
values[120]	94	1			T396	1		T807	3		T796	1
values[121]	99	1			T396	1		T807	2		T796	1
values[122]	101	1			T396	1		T807	1		T796	2
values[123]	163	1			T396	2		T807	2		T796	1
values[124]	272	1			T396	1		T807	3		T796	1
values[125]	560	1			T396	2		T807	3		T796	2
values[126]	963	1			T396	15		T807	12		T796	15
values[127]	2782	1			T396	126		T807	119		T796	123
values[128]	4775	1			T396	199		T807	275		T796	231