Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	147297	1			T80	760		T81	30		T82	74
values[2]	11569	1			T80	151		T81	2		T352	3
values[3]	4435	1			T80	125		T523	6		T399	62
values[4]	2502	1			T80	96		T523	3		T399	15
values[5]	1634	1			T80	42		T523	12		T399	8
values[6]	1094	1			T80	18		T523	4		T399	7
values[7]	702	1			T80	13		T523	3		T399	1
values[8]	678	1			T80	10		T523	4		T678	11
values[9]	505	1			T80	2		T523	5		T678	12
values[10]	477	1			T523	8		T678	18		T528	12
values[11]	438	1			T523	3		T678	23		T528	3
values[12]	403	1			T523	11		T678	16		T528	3
values[13]	373	1			T523	6		T678	9		T528	9
values[14]	392	1			T523	2		T678	8		T528	24
values[15]	364	1			T523	7		T678	9		T528	5
values[16]	324	1			T523	7		T678	11		T528	15
values[17]	304	1			T523	6		T678	24		T528	4
values[18]	362	1			T523	8		T678	10		T528	4
values[19]	303	1			T523	7		T678	8		T528	3
values[20]	323	1			T523	3		T678	16		T528	3
values[21]	296	1			T523	2		T678	11		T528	5
values[22]	316	1			T523	6		T678	13		T528	18
values[23]	278	1			T523	4		T678	15		T528	7
values[24]	293	1			T523	3		T678	17		T528	5
values[25]	282	1			T523	4		T678	15		T528	9
values[26]	282	1			T523	4		T678	6		T528	9
values[27]	283	1			T523	4		T678	14		T528	8
values[28]	337	1			T523	5		T678	9		T528	3
values[29]	365	1			T523	19		T678	22		T528	6
values[30]	306	1			T523	11		T678	18		T528	8
values[31]	332	1			T523	11		T678	28		T528	3
values[32]	310	1			T523	6		T678	13		T528	6
values[33]	250	1			T523	4		T678	11		T528	23
values[34]	296	1			T523	5		T678	20		T528	10
values[35]	284	1			T523	7		T678	11		T528	16
values[36]	296	1			T523	12		T678	14		T528	3
values[37]	324	1			T523	15		T678	25		T528	4
values[38]	303	1			T523	7		T678	9		T528	7
values[39]	284	1			T523	4		T678	19		T528	7
values[40]	306	1			T523	2		T678	8		T528	5
values[41]	272	1			T523	5		T678	7		T528	9
values[42]	284	1			T523	4		T678	16		T528	15
values[43]	283	1			T523	3		T678	19		T528	19
values[44]	282	1			T523	2		T678	11		T528	12
values[45]	319	1			T523	6		T678	9		T528	9
values[46]	270	1			T523	5		T678	19		T528	5
values[47]	231	1			T523	6		T678	10		T528	3
values[48]	260	1			T523	8		T678	15		T528	11
values[49]	238	1			T523	3		T678	7		T528	3
values[50]	214	1			T523	3		T678	8		T528	9
values[51]	270	1			T523	3		T678	24		T528	7
values[52]	269	1			T523	3		T678	10		T528	4
values[53]	278	1			T523	5		T678	14		T528	3
values[54]	285	1			T523	2		T678	5		T528	4
values[55]	251	1			T523	5		T678	10		T528	6
values[56]	261	1			T523	4		T678	21		T528	5
values[57]	262	1			T523	5		T678	12		T528	5
values[58]	276	1			T523	3		T678	8		T528	4
values[59]	248	1			T523	4		T678	11		T528	4
values[60]	210	1			T523	3		T678	9		T528	8
values[61]	271	1			T523	5		T678	9		T528	9
values[62]	219	1			T523	11		T678	10		T528	16
values[63]	240	1			T523	5		T678	19		T528	4
values[64]	216	1			T523	6		T678	26		T528	6
values[65]	212	1			T523	9		T678	16		T528	3
values[66]	240	1			T523	10		T678	10		T528	6
values[67]	222	1			T523	8		T678	13		T528	7
values[68]	184	1			T523	3		T678	9		T528	11
values[69]	177	1			T523	11		T678	6		T528	5
values[70]	196	1			T523	9		T678	20		T528	5
values[71]	169	1			T523	7		T678	14		T528	9
values[72]	135	1			T523	2		T678	8		T402	5
values[73]	124	1			T523	7		T678	15		T402	5
values[74]	167	1			T523	6		T678	14		T402	13
values[75]	129	1			T523	7		T678	11		T402	3
values[76]	136	1			T523	10		T678	8		T805	1
values[77]	128	1			T523	3		T678	11		T805	1
values[78]	121	1			T523	7		T678	8		T805	1
values[79]	102	1			T523	5		T678	1		T805	1
values[80]	120	1			T523	8		T805	1		T492	9
values[81]	156	1			T523	19		T805	1		T492	9
values[82]	169	1			T523	15		T805	1		T492	8
values[83]	152	1			T523	10		T805	1		T492	10
values[84]	154	1			T523	12		T805	1		T492	16
values[85]	145	1			T523	10		T805	1		T492	7
values[86]	113	1			T523	10		T805	6		T492	4
values[87]	146	1			T523	17		T805	4		T492	7
values[88]	131	1			T523	23		T805	8		T492	8
values[89]	153	1			T523	20		T805	2		T492	4
values[90]	131	1			T523	13		T805	1		T492	1
values[91]	132	1			T523	17		T805	1		T492	3
values[92]	127	1			T523	15		T805	1		T492	3
values[93]	134	1			T523	7		T805	1		T492	3
values[94]	116	1			T523	14		T805	3		T492	5
values[95]	129	1			T523	10		T805	2		T492	9
values[96]	99	1			T523	9		T805	2		T492	7
values[97]	96	1			T523	16		T805	3		T492	2
values[98]	107	1			T523	5		T805	3		T492	1
values[99]	116	1			T523	10		T805	2		T492	1
values[100]	85	1			T523	7		T805	1		T492	2
values[101]	95	1			T523	5		T805	2		T492	3
values[102]	118	1			T523	24		T805	1		T492	5
values[103]	118	1			T523	16		T805	5		T492	6
values[104]	99	1			T523	8		T805	2		T492	8
values[105]	70	1			T523	9		T805	2		T492	4
values[106]	99	1			T523	19		T805	2		T492	1
values[107]	107	1			T523	11		T805	3		T403	1
values[108]	109	1			T523	19		T805	2		T403	7
values[109]	100	1			T523	19		T805	1		T403	4
values[110]	95	1			T523	5		T805	2		T403	3
values[111]	92	1			T523	5		T805	3		T403	1
values[112]	92	1			T523	6		T805	6		T403	1
values[113]	80	1			T523	3		T805	6		T403	1
values[114]	83	1			T523	5		T805	1		T403	1
values[115]	84	1			T523	7		T805	2		T403	2
values[116]	79	1			T523	3		T805	4		T403	4
values[117]	84	1			T523	5		T805	2		T403	2
values[118]	87	1			T523	3		T805	2		T403	1
values[119]	76	1			T523	6		T805	3		T403	1
values[120]	79	1			T523	9		T805	3		T403	1
values[121]	85	1			T523	3		T805	1		T403	1
values[122]	73	1			T523	4		T805	1		T403	2
values[123]	71	1			T523	1		T805	1		T403	1
values[124]	66	1			T523	3		T805	5		T403	1
values[125]	82	1			T523	6		T805	1		T403	2
values[126]	170	1			T523	16		T805	4		T403	1
values[127]	810	1			T523	16		T805	32		T403	24
values[128]	6098	1			T523	7		T805	318		T403	297