Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142091	1			T80	657		T81	26		T82	78
values[2]	10341	1			T80	15		T81	4		T352	8
values[3]	4191	1			T80	1		T81	1		T352	7
values[4]	2629	1			T352	4		T396	1		T525	7
values[5]	1914	1			T352	7		T396	1		T525	9
values[6]	1412	1			T352	11		T396	1		T525	7
values[7]	1038	1			T352	5		T396	1		T525	12
values[8]	811	1			T352	4		T396	1		T525	3
values[9]	593	1			T352	4		T396	1		T525	5
values[10]	493	1			T352	7		T396	1		T525	7
values[11]	507	1			T352	8		T396	1		T525	12
values[12]	484	1			T352	3		T396	1		T525	10
values[13]	479	1			T352	6		T396	1		T525	16
values[14]	447	1			T352	13		T396	1		T525	16
values[15]	401	1			T352	6		T396	1		T525	4
values[16]	374	1			T352	9		T396	1		T525	3
values[17]	401	1			T352	9		T396	1		T525	7
values[18]	388	1			T352	7		T396	1		T525	5
values[19]	428	1			T352	6		T396	1		T525	5
values[20]	415	1			T352	3		T396	1		T525	5
values[21]	458	1			T352	4		T396	1		T525	10
values[22]	404	1			T352	5		T396	1		T525	20
values[23]	408	1			T352	12		T396	1		T525	4
values[24]	467	1			T352	4		T396	1		T525	2
values[25]	403	1			T352	9		T396	1		T525	12
values[26]	387	1			T352	7		T396	1		T525	4
values[27]	379	1			T352	11		T396	1		T525	6
values[28]	328	1			T352	6		T396	1		T525	11
values[29]	389	1			T352	6		T396	1		T525	6
values[30]	474	1			T352	7		T396	1		T525	10
values[31]	408	1			T352	17		T396	1		T525	4
values[32]	426	1			T352	5		T396	1		T525	7
values[33]	356	1			T352	5		T396	1		T525	6
values[34]	374	1			T352	5		T396	1		T525	5
values[35]	385	1			T352	13		T396	1		T525	9
values[36]	360	1			T352	22		T396	1		T525	7
values[37]	420	1			T352	13		T396	1		T525	14
values[38]	383	1			T352	10		T396	1		T525	7
values[39]	314	1			T352	14		T396	1		T525	5
values[40]	362	1			T352	9		T396	1		T525	7
values[41]	423	1			T352	5		T396	1		T525	9
values[42]	372	1			T352	4		T396	1		T525	5
values[43]	349	1			T352	5		T396	1		T525	7
values[44]	377	1			T352	7		T396	1		T525	8
values[45]	299	1			T352	2		T396	1		T525	3
values[46]	361	1			T352	7		T396	1		T525	10
values[47]	327	1			T352	6		T396	1		T525	3
values[48]	348	1			T352	5		T396	1		T525	6
values[49]	290	1			T352	5		T396	1		T525	7
values[50]	310	1			T352	9		T396	1		T525	11
values[51]	317	1			T352	5		T396	1		T525	4
values[52]	347	1			T352	8		T396	1		T525	17
values[53]	337	1			T352	6		T396	1		T525	17
values[54]	324	1			T352	3		T396	1		T525	14
values[55]	312	1			T352	15		T396	1		T525	3
values[56]	328	1			T352	10		T396	1		T525	5
values[57]	301	1			T352	7		T396	1		T525	10
values[58]	332	1			T352	7		T396	1		T525	7
values[59]	298	1			T352	3		T396	1		T525	8
values[60]	247	1			T352	5		T396	1		T525	6
values[61]	228	1			T352	7		T396	1		T525	7
values[62]	223	1			T352	7		T396	1		T525	4
values[63]	198	1			T352	11		T396	1		T525	5
values[64]	229	1			T352	8		T396	1		T525	5
values[65]	213	1			T352	4		T396	1		T525	4
values[66]	228	1			T352	14		T396	1		T525	13
values[67]	161	1			T352	5		T396	1		T525	4
values[68]	125	1			T396	1		T525	1		T795	1
values[69]	154	1			T396	1		T795	1		T440	2
values[70]	136	1			T396	1		T795	1		T440	1
values[71]	101	1			T396	1		T795	1		T440	3
values[72]	113	1			T396	1		T795	1		T440	1
values[73]	109	1			T396	1		T795	1		T440	2
values[74]	124	1			T396	1		T795	1		T440	2
values[75]	116	1			T396	1		T795	1		T440	2
values[76]	109	1			T396	1		T795	2		T440	6
values[77]	97	1			T396	2		T795	1		T440	1
values[78]	112	1			T396	1		T795	1		T440	6
values[79]	103	1			T396	1		T795	1		T440	2
values[80]	82	1			T396	1		T795	1		T440	2
values[81]	73	1			T396	1		T795	1		T440	1
values[82]	99	1			T396	1		T795	1		T440	11
values[83]	101	1			T396	1		T795	1		T440	8
values[84]	87	1			T396	1		T795	1		T440	4
values[85]	95	1			T396	1		T795	3		T440	1
values[86]	98	1			T396	1		T795	11		T440	2
values[87]	94	1			T396	1		T795	14		T440	1
values[88]	90	1			T396	1		T795	12		T440	1
values[89]	83	1			T396	1		T795	3		T440	2
values[90]	112	1			T396	1		T795	2		T440	7
values[91]	72	1			T396	1		T795	1		T440	4
values[92]	80	1			T396	1		T795	1		T440	3
values[93]	85	1			T396	1		T795	1		T440	7
values[94]	65	1			T396	1		T795	1		T440	3
values[95]	86	1			T396	1		T795	1		T440	2
values[96]	89	1			T396	1		T795	1		T440	2
values[97]	82	1			T396	1		T795	3		T440	3
values[98]	96	1			T396	1		T795	7		T440	2
values[99]	87	1			T396	1		T795	4		T440	1
values[100]	61	1			T396	1		T795	5		T440	1
values[101]	82	1			T396	1		T795	2		T440	4
values[102]	101	1			T396	1		T795	1		T440	7
values[103]	77	1			T396	1		T795	1		T440	4
values[104]	88	1			T396	1		T795	7		T440	2
values[105]	78	1			T396	1		T795	5		T440	5
values[106]	68	1			T396	1		T795	2		T440	5
values[107]	47	1			T396	1		T795	2		T440	3
values[108]	65	1			T396	1		T795	5		T800	6
values[109]	64	1			T396	1		T795	3		T800	8
values[110]	83	1			T396	1		T795	3		T800	3
values[111]	79	1			T396	1		T795	1		T800	1
values[112]	64	1			T396	1		T795	2		T800	2
values[113]	56	1			T396	1		T795	2		T800	3
values[114]	57	1			T396	1		T795	3		T800	1
values[115]	53	1			T396	1		T795	1		T800	10
values[116]	62	1			T396	1		T795	1		T800	1
values[117]	55	1			T396	1		T795	2		T800	2
values[118]	65	1			T396	1		T795	4		T800	2
values[119]	52	1			T396	1		T795	2		T800	3
values[120]	54	1			T396	1		T795	4		T800	1
values[121]	54	1			T396	1		T795	2		T800	2
values[122]	59	1			T396	1		T795	3		T800	2
values[123]	50	1			T396	1		T795	1		T800	2
values[124]	37	1			T396	1		T795	1		T800	1
values[125]	59	1			T396	3		T795	1		T800	1
values[126]	96	1			T396	5		T795	1		T800	2
values[127]	676	1			T396	37		T795	20		T800	27
values[128]	5856	1			T396	332		T795	274		T800	257