Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138831	1			T80	619		T81	32		T82	87
values[2]	9549	1			T80	7		T81	3		T352	1
values[3]	3910	1			T399	7		T396	1		T678	6
values[4]	2378	1			T396	1		T678	8		T668	56
values[5]	1490	1			T396	1		T678	10		T668	14
values[6]	1023	1			T396	1		T678	5		T621	15
values[7]	732	1			T396	1		T678	6		T621	7
values[8]	594	1			T396	1		T678	6		T621	7
values[9]	501	1			T396	1		T678	16		T621	11
values[10]	471	1			T396	1		T678	3		T621	6
values[11]	423	1			T396	1		T678	5		T621	6
values[12]	419	1			T396	1		T678	10		T621	2
values[13]	385	1			T396	1		T678	17		T621	5
values[14]	353	1			T396	1		T678	5		T621	3
values[15]	370	1			T396	1		T678	7		T621	2
values[16]	380	1			T396	1		T678	3		T621	1
values[17]	402	1			T396	1		T678	3		T621	4
values[18]	354	1			T396	1		T678	4		T796	1
values[19]	390	1			T396	1		T678	20		T796	1
values[20]	382	1			T396	1		T678	9		T796	1
values[21]	377	1			T396	1		T678	10		T796	1
values[22]	368	1			T396	1		T678	7		T796	1
values[23]	404	1			T396	1		T678	7		T796	1
values[24]	366	1			T396	1		T678	4		T796	1
values[25]	317	1			T396	1		T678	4		T796	1
values[26]	335	1			T396	1		T678	15		T796	3
values[27]	346	1			T396	1		T678	7		T796	1
values[28]	329	1			T396	1		T678	12		T796	1
values[29]	353	1			T396	1		T678	6		T796	1
values[30]	373	1			T396	1		T678	6		T796	1
values[31]	364	1			T396	1		T678	5		T796	1
values[32]	360	1			T396	1		T678	5		T796	1
values[33]	297	1			T396	1		T678	7		T796	1
values[34]	319	1			T396	1		T678	9		T796	1
values[35]	331	1			T396	1		T678	4		T796	1
values[36]	307	1			T396	1		T678	3		T796	1
values[37]	351	1			T396	1		T678	13		T796	1
values[38]	372	1			T396	1		T678	7		T796	1
values[39]	312	1			T396	1		T678	6		T796	1
values[40]	351	1			T396	1		T678	8		T796	1
values[41]	353	1			T396	1		T678	22		T796	1
values[42]	418	1			T396	1		T678	2		T796	1
values[43]	326	1			T396	1		T678	15		T796	1
values[44]	324	1			T396	1		T678	8		T796	1
values[45]	277	1			T396	1		T678	5		T796	1
values[46]	315	1			T396	1		T678	3		T796	1
values[47]	330	1			T396	1		T678	3		T796	1
values[48]	299	1			T396	1		T678	9		T796	1
values[49]	306	1			T396	1		T678	3		T796	1
values[50]	300	1			T396	1		T678	7		T796	1
values[51]	299	1			T396	1		T678	8		T796	1
values[52]	246	1			T396	1		T678	4		T796	1
values[53]	331	1			T396	1		T678	5		T796	1
values[54]	254	1			T396	1		T678	12		T796	1
values[55]	280	1			T396	1		T678	13		T796	1
values[56]	253	1			T396	1		T678	10		T796	1
values[57]	245	1			T396	2		T678	3		T796	2
values[58]	205	1			T396	1		T678	9		T796	1
values[59]	231	1			T396	1		T678	7		T796	1
values[60]	256	1			T396	1		T678	3		T796	1
values[61]	216	1			T396	1		T678	5		T796	1
values[62]	186	1			T396	1		T678	16		T796	1
values[63]	249	1			T396	1		T678	9		T796	1
values[64]	203	1			T396	1		T796	1		T500	20
values[65]	171	1			T396	1		T796	1		T500	23
values[66]	126	1			T396	1		T796	1		T500	13
values[67]	165	1			T396	1		T796	1		T500	25
values[68]	140	1			T396	1		T796	1		T500	22
values[69]	112	1			T396	7		T796	1		T500	4
values[70]	118	1			T396	10		T796	1		T500	10
values[71]	103	1			T396	5		T796	1		T500	8
values[72]	77	1			T396	4		T796	1		T500	13
values[73]	120	1			T396	9		T796	1		T500	23
values[74]	115	1			T396	16		T796	1		T500	19
values[75]	97	1			T396	4		T796	1		T500	19
values[76]	97	1			T396	3		T796	1		T500	17
values[77]	84	1			T396	3		T796	1		T500	17
values[78]	69	1			T396	2		T796	1		T500	13
values[79]	68	1			T396	4		T796	1		T500	14
values[80]	76	1			T396	5		T796	1		T500	19
values[81]	72	1			T396	5		T796	1		T500	18
values[82]	54	1			T396	3		T796	1		T500	13
values[83]	60	1			T396	5		T796	2		T500	4
values[84]	53	1			T396	5		T796	1		T500	6
values[85]	58	1			T396	1		T796	6		T500	3
values[86]	50	1			T396	1		T796	4		T500	2
values[87]	65	1			T396	1		T796	4		T500	8
values[88]	61	1			T396	4		T796	1		T500	9
values[89]	76	1			T396	4		T796	1		T500	6
values[90]	54	1			T396	1		T796	1		T500	4
values[91]	44	1			T396	3		T796	1		T500	6
values[92]	50	1			T396	2		T796	3		T500	3
values[93]	61	1			T396	1		T796	1		T500	3
values[94]	58	1			T396	4		T796	2		T500	7
values[95]	65	1			T396	1		T796	3		T500	12
values[96]	95	1			T396	3		T796	3		T500	13
values[97]	86	1			T396	1		T796	6		T500	6
values[98]	61	1			T396	2		T796	4		T500	1
values[99]	51	1			T396	2		T796	5		T640	1
values[100]	77	1			T396	1		T796	3		T640	5
values[101]	57	1			T396	2		T796	1		T640	4
values[102]	75	1			T396	1		T796	6		T640	4
values[103]	65	1			T396	1		T796	2		T640	2
values[104]	65	1			T396	4		T796	2		T640	3
values[105]	70	1			T396	1		T796	3		T640	1
values[106]	61	1			T396	1		T796	1		T640	3
values[107]	70	1			T396	1		T796	2		T640	3
values[108]	84	1			T396	1		T796	5		T640	5
values[109]	72	1			T396	1		T796	4		T640	4
values[110]	75	1			T396	2		T796	1		T640	1
values[111]	72	1			T396	1		T796	2		T640	1
values[112]	76	1			T396	5		T796	6		T640	6
values[113]	64	1			T396	3		T796	3		T640	2
values[114]	59	1			T396	3		T796	1		T640	5
values[115]	80	1			T396	5		T796	3		T640	5
values[116]	59	1			T396	1		T796	3		T640	2
values[117]	56	1			T396	1		T796	2		T640	2
values[118]	73	1			T396	1		T796	2		T640	11
values[119]	72	1			T396	1		T796	3		T640	11
values[120]	52	1			T396	3		T796	1		T640	5
values[121]	57	1			T396	1		T796	2		T640	1
values[122]	63	1			T396	1		T796	1		T640	5
values[123]	63	1			T396	2		T796	1		T640	5
values[124]	63	1			T396	1		T796	1		T640	5
values[125]	63	1			T396	1		T796	1		T640	7
values[126]	125	1			T396	2		T796	1		T640	20
values[127]	793	1			T396	29		T796	19		T640	21
values[128]	6780	1			T396	231		T796	239		T640	15