Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137564	1			T80	670		T81	27		T82	89
values[2]	8879	1			T80	10		T81	1		T82	1
values[3]	3432	1			T80	1		T352	8		T523	71
values[4]	2196	1			T352	7		T523	46		T396	1
values[5]	1430	1			T352	5		T523	26		T396	1
values[6]	863	1			T352	4		T523	8		T396	1
values[7]	675	1			T352	6		T396	1		T525	9
values[8]	541	1			T352	6		T396	1		T525	3
values[9]	475	1			T352	8		T396	1		T525	3
values[10]	453	1			T352	9		T396	1		T525	3
values[11]	356	1			T352	10		T396	1		T525	6
values[12]	349	1			T352	19		T396	1		T525	21
values[13]	314	1			T352	6		T396	1		T525	8
values[14]	332	1			T352	18		T396	1		T525	7
values[15]	293	1			T352	9		T396	1		T525	5
values[16]	273	1			T352	2		T396	1		T525	5
values[17]	327	1			T352	7		T396	1		T525	10
values[18]	283	1			T352	7		T396	1		T525	8
values[19]	250	1			T352	6		T396	1		T525	5
values[20]	252	1			T352	2		T396	1		T525	5
values[21]	250	1			T352	5		T396	1		T525	6
values[22]	261	1			T352	4		T396	1		T525	4
values[23]	255	1			T352	5		T396	1		T525	14
values[24]	295	1			T352	4		T396	1		T525	8
values[25]	281	1			T352	4		T396	1		T525	7
values[26]	272	1			T352	8		T396	1		T525	5
values[27]	276	1			T352	9		T396	1		T525	5
values[28]	239	1			T352	13		T396	1		T525	3
values[29]	201	1			T352	7		T396	1		T525	4
values[30]	223	1			T352	6		T396	1		T525	14
values[31]	256	1			T352	3		T396	1		T525	16
values[32]	271	1			T352	7		T396	1		T525	10
values[33]	265	1			T352	14		T396	1		T525	7
values[34]	245	1			T352	3		T396	1		T525	6
values[35]	296	1			T352	7		T396	1		T525	16
values[36]	220	1			T352	9		T396	1		T525	5
values[37]	254	1			T352	7		T396	1		T525	13
values[38]	245	1			T352	17		T396	1		T525	7
values[39]	299	1			T352	19		T396	1		T525	5
values[40]	248	1			T352	5		T396	1		T525	4
values[41]	271	1			T352	5		T396	1		T525	8
values[42]	228	1			T352	9		T396	1		T525	7
values[43]	268	1			T352	9		T396	1		T525	7
values[44]	262	1			T352	16		T396	1		T525	4
values[45]	227	1			T352	6		T396	1		T403	1
values[46]	252	1			T352	5		T396	1		T403	1
values[47]	212	1			T352	4		T396	1		T403	1
values[48]	213	1			T352	4		T396	1		T403	1
values[49]	210	1			T352	6		T396	1		T403	1
values[50]	236	1			T352	5		T396	1		T403	1
values[51]	229	1			T352	10		T396	1		T403	1
values[52]	240	1			T352	13		T396	1		T403	1
values[53]	191	1			T352	12		T396	1		T403	1
values[54]	213	1			T352	7		T396	1		T403	1
values[55]	214	1			T352	4		T396	1		T403	1
values[56]	181	1			T396	1		T403	1		T806	1
values[57]	189	1			T396	1		T403	1		T806	1
values[58]	138	1			T396	1		T403	1		T806	1
values[59]	171	1			T396	1		T403	1		T806	2
values[60]	151	1			T396	1		T403	1		T806	1
values[61]	143	1			T396	1		T403	1		T806	1
values[62]	166	1			T396	1		T403	1		T806	1
values[63]	151	1			T396	1		T403	1		T806	1
values[64]	141	1			T396	1		T403	1		T806	1
values[65]	134	1			T396	1		T403	1		T806	1
values[66]	116	1			T396	1		T403	1		T806	1
values[67]	135	1			T396	1		T403	1		T806	1
values[68]	87	1			T396	1		T403	1		T806	1
values[69]	81	1			T396	1		T403	1		T806	1
values[70]	86	1			T396	1		T403	1		T806	1
values[71]	88	1			T396	1		T403	1		T806	1
values[72]	72	1			T396	2		T403	1		T806	1
values[73]	64	1			T396	2		T403	1		T806	1
values[74]	68	1			T396	1		T403	1		T806	1
values[75]	58	1			T396	1		T403	1		T806	1
values[76]	47	1			T396	1		T403	1		T806	1
values[77]	47	1			T396	1		T403	1		T806	1
values[78]	48	1			T396	1		T403	1		T806	1
values[79]	52	1			T396	1		T403	1		T806	1
values[80]	53	1			T396	1		T403	1		T806	1
values[81]	55	1			T396	1		T403	1		T806	1
values[82]	57	1			T396	1		T403	1		T806	1
values[83]	56	1			T396	1		T403	1		T806	1
values[84]	60	1			T396	1		T403	1		T806	1
values[85]	55	1			T396	1		T403	1		T806	1
values[86]	60	1			T396	1		T403	1		T806	1
values[87]	63	1			T396	1		T403	1		T806	1
values[88]	65	1			T396	1		T403	1		T806	1
values[89]	53	1			T396	1		T403	1		T806	1
values[90]	51	1			T396	1		T403	1		T806	1
values[91]	58	1			T396	1		T403	1		T806	1
values[92]	63	1			T396	1		T403	1		T806	1
values[93]	50	1			T396	1		T403	1		T806	1
values[94]	53	1			T396	1		T403	1		T806	1
values[95]	48	1			T396	1		T403	1		T806	1
values[96]	73	1			T396	1		T403	1		T806	1
values[97]	76	1			T396	1		T403	2		T806	1
values[98]	88	1			T396	1		T403	1		T806	1
values[99]	77	1			T396	1		T403	1		T806	1
values[100]	70	1			T396	1		T403	1		T806	1
values[101]	59	1			T396	1		T403	1		T806	1
values[102]	64	1			T396	1		T403	1		T806	1
values[103]	61	1			T396	1		T403	1		T806	1
values[104]	61	1			T396	1		T403	1		T806	1
values[105]	51	1			T396	1		T403	1		T806	1
values[106]	82	1			T396	1		T403	1		T806	1
values[107]	70	1			T396	1		T403	1		T806	1
values[108]	53	1			T396	1		T403	1		T806	1
values[109]	56	1			T396	1		T403	1		T806	1
values[110]	72	1			T396	1		T403	1		T806	1
values[111]	52	1			T396	1		T403	1		T806	1
values[112]	46	1			T396	1		T403	1		T806	1
values[113]	54	1			T396	1		T403	1		T806	1
values[114]	66	1			T396	1		T403	1		T806	1
values[115]	56	1			T396	1		T403	1		T806	1
values[116]	55	1			T396	1		T403	1		T806	1
values[117]	74	1			T396	1		T403	5		T806	1
values[118]	80	1			T396	1		T403	1		T806	1
values[119]	73	1			T396	1		T403	2		T806	1
values[120]	72	1			T396	3		T403	2		T806	1
values[121]	53	1			T396	2		T403	1		T806	2
values[122]	64	1			T396	1		T403	1		T806	2
values[123]	80	1			T396	1		T403	2		T806	1
values[124]	82	1			T396	2		T403	1		T806	1
values[125]	87	1			T396	1		T403	1		T806	3
values[126]	154	1			T396	1		T403	3		T806	2
values[127]	863	1			T396	35		T403	42		T806	30
values[128]	7305	1			T396	371		T403	404		T806	363