Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143358	1			T80	640		T81	29		T82	99
values[2]	11528	1			T80	23		T352	2		T430	1
values[3]	4283	1			T80	9		T399	2		T396	1
values[4]	2469	1			T80	3		T396	1		T807	1
values[5]	1543	1			T396	1		T807	1		T402	3
values[6]	1079	1			T396	1		T807	1		T402	4
values[7]	875	1			T396	1		T807	1		T402	5
values[8]	613	1			T396	1		T807	1		T402	8
values[9]	496	1			T396	1		T807	1		T402	10
values[10]	451	1			T396	1		T807	1		T402	12
values[11]	415	1			T396	1		T807	1		T402	6
values[12]	360	1			T396	1		T807	1		T402	5
values[13]	305	1			T396	1		T807	1		T402	4
values[14]	311	1			T396	1		T807	1		T402	5
values[15]	319	1			T396	1		T807	1		T402	5
values[16]	305	1			T396	1		T807	1		T402	14
values[17]	316	1			T396	1		T807	1		T402	13
values[18]	309	1			T396	1		T807	1		T402	6
values[19]	235	1			T396	1		T807	1		T402	9
values[20]	291	1			T396	1		T807	1		T402	4
values[21]	284	1			T396	1		T807	1		T402	4
values[22]	262	1			T396	1		T807	1		T402	8
values[23]	284	1			T396	1		T807	1		T402	11
values[24]	319	1			T396	1		T807	1		T402	10
values[25]	285	1			T396	1		T807	1		T402	5
values[26]	283	1			T396	1		T807	1		T402	8
values[27]	246	1			T396	1		T807	1		T402	4
values[28]	275	1			T396	1		T807	1		T402	7
values[29]	225	1			T396	1		T807	1		T402	6
values[30]	246	1			T396	1		T807	1		T402	5
values[31]	246	1			T396	1		T807	1		T402	11
values[32]	298	1			T396	1		T807	1		T402	22
values[33]	303	1			T396	1		T807	1		T402	18
values[34]	280	1			T396	1		T807	1		T402	7
values[35]	259	1			T396	1		T807	2		T402	14
values[36]	245	1			T396	1		T807	1		T402	7
values[37]	289	1			T396	1		T807	1		T402	8
values[38]	252	1			T396	1		T807	1		T402	8
values[39]	296	1			T396	1		T807	1		T402	3
values[40]	214	1			T396	1		T807	1		T402	7
values[41]	237	1			T396	1		T807	1		T402	5
values[42]	257	1			T396	1		T807	1		T402	5
values[43]	281	1			T396	1		T807	1		T402	3
values[44]	235	1			T396	1		T807	1		T402	5
values[45]	234	1			T396	1		T807	1		T402	3
values[46]	234	1			T396	1		T807	1		T402	4
values[47]	254	1			T396	1		T807	1		T402	8
values[48]	211	1			T396	1		T807	1		T402	7
values[49]	230	1			T396	1		T807	1		T402	4
values[50]	274	1			T396	1		T807	1		T402	5
values[51]	239	1			T396	1		T807	1		T402	7
values[52]	244	1			T396	1		T807	1		T402	8
values[53]	211	1			T396	2		T807	1		T402	5
values[54]	196	1			T396	1		T807	1		T402	7
values[55]	231	1			T396	1		T807	1		T402	12
values[56]	244	1			T396	1		T807	1		T402	6
values[57]	243	1			T396	1		T807	1		T402	4
values[58]	244	1			T396	1		T807	1		T402	5
values[59]	220	1			T396	1		T807	1		T402	8
values[60]	212	1			T396	1		T807	1		T402	13
values[61]	191	1			T396	1		T807	1		T402	5
values[62]	205	1			T396	1		T807	1		T402	10
values[63]	229	1			T396	1		T807	1		T402	10
values[64]	211	1			T396	1		T807	1		T402	9
values[65]	186	1			T396	1		T807	1		T402	2
values[66]	149	1			T396	1		T807	1		T795	1
values[67]	139	1			T396	1		T807	1		T795	1
values[68]	117	1			T396	1		T807	1		T795	1
values[69]	106	1			T396	1		T807	1		T795	1
values[70]	92	1			T396	1		T807	1		T795	1
values[71]	77	1			T396	1		T807	1		T795	1
values[72]	96	1			T396	1		T807	1		T795	1
values[73]	92	1			T396	1		T807	1		T795	1
values[74]	86	1			T396	1		T807	1		T795	1
values[75]	98	1			T396	1		T807	1		T795	1
values[76]	85	1			T396	1		T807	1		T795	1
values[77]	69	1			T396	1		T807	1		T795	1
values[78]	72	1			T396	1		T807	1		T795	1
values[79]	65	1			T396	1		T807	1		T795	1
values[80]	66	1			T396	1		T807	1		T795	1
values[81]	93	1			T396	1		T807	1		T795	1
values[82]	91	1			T396	1		T807	1		T795	1
values[83]	66	1			T396	1		T807	1		T795	1
values[84]	76	1			T396	1		T807	1		T795	1
values[85]	91	1			T396	1		T807	1		T795	1
values[86]	90	1			T396	1		T807	1		T795	1
values[87]	77	1			T396	1		T807	1		T795	1
values[88]	86	1			T396	1		T807	1		T795	1
values[89]	80	1			T396	1		T807	1		T795	1
values[90]	81	1			T396	1		T807	1		T795	1
values[91]	60	1			T396	1		T807	1		T795	1
values[92]	76	1			T396	1		T807	1		T795	2
values[93]	73	1			T396	1		T807	1		T795	2
values[94]	87	1			T396	1		T807	1		T795	1
values[95]	63	1			T396	1		T807	1		T795	1
values[96]	92	1			T396	1		T807	1		T795	1
values[97]	85	1			T396	1		T807	1		T795	5
values[98]	61	1			T396	1		T807	1		T795	1
values[99]	62	1			T396	1		T807	1		T795	2
values[100]	83	1			T396	1		T807	1		T795	3
values[101]	82	1			T396	1		T807	1		T795	4
values[102]	83	1			T396	1		T807	1		T795	7
values[103]	77	1			T396	1		T807	1		T795	2
values[104]	69	1			T396	1		T807	1		T795	1
values[105]	79	1			T396	1		T807	1		T795	3
values[106]	65	1			T396	1		T807	1		T795	4
values[107]	57	1			T396	1		T807	1		T795	3
values[108]	83	1			T396	1		T807	1		T795	2
values[109]	72	1			T396	1		T807	2		T795	1
values[110]	63	1			T396	1		T807	3		T795	1
values[111]	75	1			T396	2		T807	2		T795	1
values[112]	110	1			T396	1		T807	4		T795	4
values[113]	91	1			T396	2		T807	4		T795	1
values[114]	84	1			T396	2		T807	1		T795	1
values[115]	94	1			T396	9		T807	3		T795	1
values[116]	81	1			T396	2		T807	3		T795	5
values[117]	78	1			T396	3		T807	6		T795	3
values[118]	76	1			T396	1		T807	1		T795	1
values[119]	66	1			T396	2		T807	2		T795	3
values[120]	93	1			T396	2		T807	3		T795	2
values[121]	91	1			T396	1		T807	3		T795	1
values[122]	63	1			T396	1		T807	1		T795	3
values[123]	79	1			T396	2		T807	4		T795	5
values[124]	72	1			T396	1		T807	1		T795	1
values[125]	107	1			T396	1		T807	3		T795	2
values[126]	168	1			T396	3		T807	2		T795	4
values[127]	748	1			T396	27		T807	30		T795	34
values[128]	5902	1			T396	320		T807	316		T795	273