Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144105	1			T80	898		T81	33		T82	97
values[2]	10188	1			T80	145		T430	2		T399	99
values[3]	3541	1			T80	65		T399	106		T396	1
values[4]	2057	1			T80	25		T399	78		T396	1
values[5]	1365	1			T80	25		T399	63		T396	1
values[6]	861	1			T80	2		T399	35		T396	1
values[7]	562	1			T399	8		T396	1		T528	6
values[8]	398	1			T399	6		T396	1		T621	8
values[9]	326	1			T399	3		T396	1		T403	2
values[10]	378	1			T396	1		T403	2		T615	6
values[11]	275	1			T396	1		T403	2		T615	3
values[12]	253	1			T396	1		T403	2		T615	5
values[13]	285	1			T396	1		T403	2		T615	4
values[14]	273	1			T396	1		T403	2		T615	9
values[15]	256	1			T396	1		T403	2		T615	8
values[16]	265	1			T396	1		T403	2		T615	6
values[17]	291	1			T396	1		T403	2		T615	7
values[18]	300	1			T396	1		T403	2		T615	7
values[19]	253	1			T396	1		T403	2		T615	5
values[20]	262	1			T396	1		T403	2		T615	5
values[21]	333	1			T396	1		T403	2		T615	6
values[22]	280	1			T396	1		T403	2		T615	12
values[23]	248	1			T396	1		T403	2		T615	6
values[24]	284	1			T396	1		T403	2		T615	10
values[25]	220	1			T396	2		T403	2		T615	2
values[26]	244	1			T396	1		T403	2		T615	11
values[27]	214	1			T396	1		T403	2		T615	8
values[28]	253	1			T396	1		T403	2		T615	12
values[29]	244	1			T396	1		T403	2		T615	7
values[30]	233	1			T396	1		T403	2		T615	9
values[31]	219	1			T396	1		T403	2		T615	8
values[32]	229	1			T396	1		T403	2		T615	7
values[33]	249	1			T396	1		T403	2		T615	13
values[34]	239	1			T396	1		T403	2		T615	5
values[35]	234	1			T396	1		T403	2		T615	4
values[36]	211	1			T396	1		T403	2		T615	4
values[37]	251	1			T396	1		T403	2		T615	7
values[38]	200	1			T396	1		T403	2		T615	10
values[39]	192	1			T396	1		T403	2		T615	6
values[40]	191	1			T396	1		T403	2		T615	5
values[41]	234	1			T396	1		T403	2		T615	10
values[42]	257	1			T396	1		T403	2		T615	8
values[43]	243	1			T396	2		T403	2		T615	9
values[44]	203	1			T396	1		T403	2		T615	6
values[45]	209	1			T396	1		T403	2		T615	4
values[46]	196	1			T396	1		T403	2		T615	3
values[47]	235	1			T396	1		T403	2		T615	7
values[48]	193	1			T396	1		T403	2		T615	7
values[49]	204	1			T396	1		T403	2		T615	7
values[50]	222	1			T396	1		T403	2		T615	9
values[51]	193	1			T396	1		T403	2		T615	13
values[52]	203	1			T396	1		T403	2		T615	6
values[53]	255	1			T396	1		T403	3		T615	19
values[54]	266	1			T396	1		T403	2		T615	17
values[55]	216	1			T396	1		T403	2		T615	12
values[56]	202	1			T396	1		T403	2		T615	4
values[57]	195	1			T396	1		T403	2		T615	4
values[58]	229	1			T396	1		T403	2		T615	5
values[59]	162	1			T396	1		T403	2		T615	4
values[60]	163	1			T396	1		T403	2		T615	2
values[61]	121	1			T396	1		T403	2		T615	5
values[62]	135	1			T396	1		T403	2		T615	11
values[63]	146	1			T396	1		T403	2		T615	6
values[64]	118	1			T396	1		T403	2		T615	4
values[65]	86	1			T396	1		T403	2		T615	5
values[66]	81	1			T396	1		T403	2		T615	10
values[67]	71	1			T396	1		T403	2		T615	3
values[68]	90	1			T396	1		T403	2		T615	10
values[69]	96	1			T396	1		T403	2		T615	11
values[70]	71	1			T396	1		T403	2		T615	6
values[71]	54	1			T396	1		T403	2		T500	3
values[72]	47	1			T396	1		T403	2		T500	1
values[73]	55	1			T396	1		T403	2		T500	2
values[74]	57	1			T396	1		T403	2		T500	1
values[75]	54	1			T396	1		T403	2		T500	2
values[76]	52	1			T396	1		T403	2		T500	1
values[77]	65	1			T396	1		T403	2		T500	2
values[78]	50	1			T396	1		T403	2		T500	9
values[79]	53	1			T396	1		T403	2		T500	10
values[80]	39	1			T396	1		T403	2		T500	5
values[81]	45	1			T396	1		T403	2		T500	11
values[82]	45	1			T396	1		T403	2		T500	16
values[83]	38	1			T396	1		T403	2		T500	3
values[84]	52	1			T396	1		T403	2		T500	7
values[85]	43	1			T396	1		T403	2		T500	6
values[86]	53	1			T396	1		T403	2		T500	8
values[87]	51	1			T396	1		T403	3		T500	3
values[88]	50	1			T396	1		T403	4		T500	4
values[89]	51	1			T396	1		T403	5		T500	5
values[90]	50	1			T396	1		T403	3		T500	7
values[91]	56	1			T396	1		T403	3		T500	10
values[92]	52	1			T396	1		T403	7		T500	7
values[93]	46	1			T396	1		T403	3		T500	8
values[94]	48	1			T396	1		T403	6		T500	2
values[95]	52	1			T396	1		T403	8		T500	5
values[96]	43	1			T396	1		T403	6		T500	1
values[97]	50	1			T396	1		T403	3		T500	3
values[98]	42	1			T396	1		T403	2		T500	2
values[99]	38	1			T396	1		T403	3		T500	1
values[100]	62	1			T396	1		T403	2		T500	4
values[101]	55	1			T396	1		T403	3		T500	2
values[102]	55	1			T396	1		T403	3		T500	7
values[103]	59	1			T396	2		T403	5		T500	7
values[104]	57	1			T396	1		T403	3		T500	8
values[105]	42	1			T396	2		T403	2		T500	4
values[106]	38	1			T396	3		T403	3		T500	4
values[107]	43	1			T396	3		T403	3		T500	2
values[108]	58	1			T396	5		T403	2		T500	6
values[109]	58	1			T396	3		T403	7		T500	3
values[110]	63	1			T396	6		T403	4		T500	11
values[111]	69	1			T396	3		T403	5		T500	8
values[112]	71	1			T396	3		T403	9		T500	2
values[113]	61	1			T396	8		T403	3		T500	7
values[114]	43	1			T396	4		T403	2		T500	2
values[115]	49	1			T396	2		T403	2		T500	8
values[116]	44	1			T396	1		T403	5		T500	3
values[117]	42	1			T396	8		T403	3		T500	3
values[118]	47	1			T396	4		T403	2		T500	3
values[119]	43	1			T396	1		T403	2		T500	8
values[120]	46	1			T396	1		T403	2		T500	3
values[121]	53	1			T396	1		T403	7		T500	7
values[122]	55	1			T396	1		T403	6		T500	7
values[123]	50	1			T396	2		T403	5		T500	1
values[124]	45	1			T396	1		T403	5		T814	1
values[125]	44	1			T396	2		T403	4		T814	4
values[126]	59	1			T396	1		T403	8		T814	2
values[127]	512	1			T396	11		T403	55		T814	24
values[128]	4655	1			T396	247		T403	577		T814	260