Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	165128	1			T80	1223		T81	32		T82	82
values[2]	5112	1			T80	149		T81	2		T239	1
values[3]	2502	1			T80	85		T523	8		T396	1
values[4]	1962	1			T80	63		T523	5		T396	1
values[5]	1664	1			T80	57		T523	3		T396	1
values[6]	1418	1			T80	55		T523	24		T396	1
values[7]	1400	1			T80	43		T523	12		T396	1
values[8]	1129	1			T80	18		T523	9		T396	1
values[9]	912	1			T80	1		T523	10		T396	1
values[10]	851	1			T523	9		T396	1		T440	32
values[11]	721	1			T523	8		T396	1		T440	23
values[12]	639	1			T523	3		T396	1		T440	25
values[13]	560	1			T523	4		T396	1		T440	7
values[14]	559	1			T523	15		T396	1		T440	8
values[15]	460	1			T523	8		T396	1		T440	9
values[16]	489	1			T523	1		T396	1		T440	20
values[17]	464	1			T523	2		T396	1		T440	26
values[18]	419	1			T523	2		T396	1		T440	51
values[19]	403	1			T523	2		T396	1		T440	64
values[20]	345	1			T523	2		T396	1		T440	57
values[21]	289	1			T523	2		T396	1		T440	42
values[22]	282	1			T523	2		T396	1		T440	40
values[23]	310	1			T523	3		T396	1		T440	21
values[24]	311	1			T523	3		T396	1		T440	24
values[25]	315	1			T523	6		T396	1		T440	23
values[26]	274	1			T523	3		T396	1		T440	12
values[27]	293	1			T523	8		T396	1		T440	2
values[28]	291	1			T523	9		T396	1		T796	1
values[29]	250	1			T523	9		T396	1		T796	1
values[30]	159	1			T523	7		T396	1		T796	1
values[31]	142	1			T523	4		T396	1		T796	1
values[32]	116	1			T523	4		T396	1		T796	1
values[33]	111	1			T523	5		T396	1		T796	1
values[34]	88	1			T523	3		T396	1		T796	1
values[35]	63	1			T523	6		T396	1		T796	1
values[36]	64	1			T523	13		T396	1		T796	1
values[37]	91	1			T523	24		T396	1		T796	1
values[38]	89	1			T523	21		T396	1		T796	1
values[39]	70	1			T523	7		T396	1		T796	1
values[40]	72	1			T523	11		T396	1		T796	1
values[41]	56	1			T523	2		T396	1		T796	1
values[42]	66	1			T523	8		T396	1		T796	1
values[43]	63	1			T523	7		T396	1		T796	1
values[44]	63	1			T523	17		T396	1		T796	1
values[45]	61	1			T523	17		T396	1		T796	1
values[46]	76	1			T523	26		T396	1		T796	1
values[47]	67	1			T523	18		T396	1		T796	1
values[48]	63	1			T523	13		T396	1		T796	1
values[49]	79	1			T523	25		T396	1		T796	1
values[50]	71	1			T523	16		T396	1		T796	1
values[51]	65	1			T523	11		T396	1		T796	1
values[52]	64	1			T523	14		T396	1		T796	1
values[53]	61	1			T523	10		T396	1		T796	1
values[54]	63	1			T523	7		T396	1		T796	1
values[55]	65	1			T523	14		T396	1		T796	1
values[56]	63	1			T523	10		T396	1		T796	1
values[57]	64	1			T523	5		T396	1		T796	1
values[58]	62	1			T523	1		T396	1		T796	1
values[59]	53	1			T396	1		T796	1		T798	1
values[60]	50	1			T396	1		T796	1		T798	1
values[61]	53	1			T396	1		T796	1		T798	1
values[62]	54	1			T396	1		T796	1		T798	1
values[63]	59	1			T396	1		T796	1		T798	1
values[64]	54	1			T396	1		T796	1		T798	1
values[65]	49	1			T396	1		T796	1		T798	1
values[66]	49	1			T396	1		T796	1		T798	1
values[67]	49	1			T396	1		T796	1		T798	1
values[68]	53	1			T396	1		T796	1		T798	1
values[69]	63	1			T396	1		T796	1		T798	1
values[70]	53	1			T396	1		T796	1		T798	1
values[71]	45	1			T396	1		T796	1		T798	1
values[72]	49	1			T396	1		T796	1		T798	1
values[73]	52	1			T396	1		T796	1		T798	1
values[74]	63	1			T396	1		T796	1		T798	1
values[75]	64	1			T396	1		T796	1		T798	1
values[76]	72	1			T396	1		T796	1		T798	1
values[77]	58	1			T396	1		T796	1		T798	1
values[78]	56	1			T396	1		T796	1		T798	1
values[79]	70	1			T396	1		T796	1		T798	1
values[80]	67	1			T396	1		T796	1		T798	1
values[81]	70	1			T396	1		T796	1		T798	1
values[82]	68	1			T396	1		T796	1		T798	1
values[83]	79	1			T396	1		T796	1		T798	1
values[84]	75	1			T396	1		T796	1		T798	2
values[85]	68	1			T396	1		T796	1		T798	1
values[86]	74	1			T396	1		T796	1		T798	1
values[87]	66	1			T396	1		T796	1		T798	2
values[88]	78	1			T396	1		T796	1		T798	4
values[89]	72	1			T396	1		T796	1		T798	2
values[90]	75	1			T396	1		T796	1		T798	1
values[91]	62	1			T396	1		T796	1		T798	1
values[92]	67	1			T396	1		T796	1		T798	2
values[93]	69	1			T396	1		T796	1		T798	1
values[94]	80	1			T396	1		T796	1		T798	2
values[95]	81	1			T396	2		T796	1		T798	1
values[96]	74	1			T396	4		T796	1		T798	2
values[97]	85	1			T396	6		T796	1		T798	4
values[98]	78	1			T396	3		T796	1		T798	6
values[99]	95	1			T396	5		T796	1		T798	2
values[100]	78	1			T396	3		T796	1		T798	3
values[101]	75	1			T396	1		T796	1		T798	1
values[102]	72	1			T396	1		T796	1		T798	1
values[103]	91	1			T396	1		T796	1		T798	1
values[104]	101	1			T396	2		T796	1		T798	8
values[105]	91	1			T396	2		T796	1		T798	1
values[106]	96	1			T396	2		T796	1		T798	2
values[107]	95	1			T396	2		T796	1		T798	1
values[108]	84	1			T396	1		T796	1		T798	1
values[109]	74	1			T396	1		T796	1		T798	2
values[110]	91	1			T396	2		T796	1		T798	3
values[111]	100	1			T396	1		T796	1		T798	4
values[112]	89	1			T396	1		T796	1		T798	2
values[113]	89	1			T396	1		T796	3		T798	2
values[114]	90	1			T396	1		T796	2		T798	3
values[115]	101	1			T396	2		T796	4		T798	2
values[116]	96	1			T396	3		T796	3		T798	3
values[117]	94	1			T396	4		T796	5		T798	2
values[118]	108	1			T396	2		T796	1		T798	4
values[119]	97	1			T396	2		T796	1		T798	1
values[120]	84	1			T396	1		T796	1		T798	4
values[121]	103	1			T396	3		T796	1		T798	3
values[122]	103	1			T396	6		T796	3		T798	1
values[123]	119	1			T396	3		T796	2		T798	1
values[124]	193	1			T396	2		T796	1		T798	2
values[125]	361	1			T396	2		T796	2		T798	1
values[126]	753	1			T396	15		T796	22		T798	7
values[127]	3210	1			T396	95		T796	156		T798	89
values[128]	5771	1			T396	199		T796	249		T798	194